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https://github.com/brain-hackers/u-boot-brain
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99f8ad7321
This change switches all existing users of ast2500 Watchdog to Driver Model based Watchdog driver. To perform system reset Sysreset Driver uses first Watchdog device found via uclass_first_device call. Since the system is going to be reset anyway it does not make much difference which watchdog is used. Instead of using Watchdog to reset itself, SDRAM driver now uses Reset driver to do that. These were the only users of the old Watchdog API, so that API is removed. This all is done in one change to avoid having to maintain dual API for watchdog in between. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
106 lines
2.8 KiB
C
106 lines
2.8 KiB
C
/*
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* (C) Copyright 2016 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_WDT_H
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#define _ASM_ARCH_WDT_H
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#define WDT_BASE 0x1e785000
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/*
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* Special value that needs to be written to counter_restart register to
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* (re)start the timer
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*/
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#define WDT_COUNTER_RESTART_VAL 0x4755
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/* Control register */
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#define WDT_CTRL_RESET_MODE_SHIFT 5
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#define WDT_CTRL_RESET_MODE_MASK 3
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#define WDT_CTRL_EN (1 << 0)
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#define WDT_CTRL_RESET (1 << 1)
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#define WDT_CTRL_CLK1MHZ (1 << 4)
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#define WDT_CTRL_2ND_BOOT (1 << 7)
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/* Values for Reset Mode */
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#define WDT_CTRL_RESET_SOC 0
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#define WDT_CTRL_RESET_CHIP 1
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#define WDT_CTRL_RESET_CPU 2
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#define WDT_CTRL_RESET_MASK 3
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/* Reset Mask register */
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#define WDT_RESET_ARM (1 << 0)
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#define WDT_RESET_COPROC (1 << 1)
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#define WDT_RESET_SDRAM (1 << 2)
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#define WDT_RESET_AHB (1 << 3)
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#define WDT_RESET_I2C (1 << 4)
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#define WDT_RESET_MAC1 (1 << 5)
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#define WDT_RESET_MAC2 (1 << 6)
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#define WDT_RESET_GCRT (1 << 7)
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#define WDT_RESET_USB20 (1 << 8)
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#define WDT_RESET_USB11_HOST (1 << 9)
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#define WDT_RESET_USB11_EHCI2 (1 << 10)
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#define WDT_RESET_VIDEO (1 << 11)
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#define WDT_RESET_HAC (1 << 12)
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#define WDT_RESET_LPC (1 << 13)
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#define WDT_RESET_SDSDIO (1 << 14)
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#define WDT_RESET_MIC (1 << 15)
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#define WDT_RESET_CRT2C (1 << 16)
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#define WDT_RESET_PWM (1 << 17)
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#define WDT_RESET_PECI (1 << 18)
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#define WDT_RESET_JTAG (1 << 19)
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#define WDT_RESET_ADC (1 << 20)
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#define WDT_RESET_GPIO (1 << 21)
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#define WDT_RESET_MCTP (1 << 22)
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#define WDT_RESET_XDMA (1 << 23)
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#define WDT_RESET_SPI (1 << 24)
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#define WDT_RESET_MISC (1 << 25)
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#ifndef __ASSEMBLY__
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struct ast_wdt {
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u32 counter_status;
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u32 counter_reload_val;
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u32 counter_restart;
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u32 ctrl;
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u32 timeout_status;
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u32 clr_timeout_status;
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u32 reset_width;
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/* On pre-ast2500 SoCs this register is reserved. */
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u32 reset_mask;
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};
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/**
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* Given flags parameter passed to wdt_reset or wdt_start uclass functions,
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* gets Reset Mode value from it.
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*
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* @flags: flags parameter passed into wdt_reset or wdt_start
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* @return Reset Mode value
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*/
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u32 ast_reset_mode_from_flags(ulong flags);
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/**
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* Given flags parameter passed to wdt_reset or wdt_start uclass functions,
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* gets Reset Mask value from it. Reset Mask is only supported on ast2500
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*
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* @flags: flags parameter passed into wdt_reset or wdt_start
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* @return Reset Mask value
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*/
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u32 ast_reset_mask_from_flags(ulong flags);
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/**
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* Given Reset Mask and Reset Mode values, converts them to flags,
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* suitable for passing into wdt_start or wdt_reset uclass functions.
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*
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* On ast2500 Reset Mask is 25 bits wide and Reset Mode is 2 bits wide, so they
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* can both be packed into single 32 bits wide value.
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*
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* @reset_mode: Reset Mode
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* @reset_mask: Reset Mask
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*/
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ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask);
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_ARCH_WDT_H */
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