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https://github.com/brain-hackers/u-boot-brain
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4697abea62
Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org>
55 lines
1.2 KiB
C
55 lines
1.2 KiB
C
/*
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* Copyright (c) 2016 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_TIMER_H
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#define _ASM_ARCH_TIMER_H
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/* Each timer has 4 control bits in ctrl1 register.
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* Timer1 uses bits 0:3, Timer2 uses bits 4:7 and so on,
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* such that timer X uses bits (4 * X - 4):(4 * X - 1)
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* If the timer does not support PWM, bit 4 is reserved.
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*/
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#define AST_TMC_EN (1 << 0)
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#define AST_TMC_1MHZ (1 << 1)
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#define AST_TMC_OVFINTR (1 << 2)
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#define AST_TMC_PWM (1 << 3)
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/* Timers are counted from 1 in the datasheet. */
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#define AST_TMC_CTRL1_SHIFT(n) (4 * ((n) - 1))
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#define AST_TMC_RATE (1000*1000)
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#ifndef __ASSEMBLY__
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/*
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* All timers share control registers, which makes it harder to make them
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* separate devices. Since only one timer is needed at the moment, making
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* it this just one device.
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*/
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struct ast_timer_counter {
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u32 status;
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u32 reload_val;
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u32 match1;
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u32 match2;
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};
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struct ast_timer {
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struct ast_timer_counter timers1[3];
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u32 ctrl1;
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u32 ctrl2;
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#ifdef CONFIG_ASPEED_AST2500
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u32 ctrl3;
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u32 ctrl1_clr;
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#else
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u32 reserved[2];
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#endif
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struct ast_timer_counter timers2[5];
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};
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_ARCH_TIMER_H */
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