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https://github.com/brain-hackers/u-boot-brain
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8627733941
The ti816x/am389x SoC is the first generation in what U-Boot calls the "am33xx" family. In the first generation of this family the DDR initialization sequence is quite different from all of the subsequent generations. Whereas with ti814x (second generation) we can easily work the minor differenced between that and am33xx (third generation), our attempts to do this for ti816x weren't sufficient. Rather than add a large amount of #ifdef logic to make this different sequence work we add a new file, ti816x_emif4.c to handle the various required undocumented register writes and sequence and leverage what we can from arch/arm/mach-omap2/am33xx/ddr.c still. As DDR2 has similar problems today but I am unable to test it, we drop the DDR2 defines from the code rather than imply that it works by leaving it. We also remove a bunch of other untested code about changing the speed the DDR runs at. Signed-off-by: Tom Rini <trini@konsulko.com>
37 lines
815 B
C
37 lines
815 B
C
/*
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* clocks_am33xx.h
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*
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* AM33xx clock define
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CLOCKS_AM33XX_H_
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#define _CLOCKS_AM33XX_H_
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/* MAIN PLL Fdll supported frequencies */
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#define MPUPLL_M_1000 1000
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#define MPUPLL_M_800 800
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#define MPUPLL_M_720 720
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#define MPUPLL_M_600 600
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#define MPUPLL_M_500 500
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#define MPUPLL_M_300 300
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#define UART_RESET (0x1 << 1)
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#define UART_CLK_RUNNING_MASK 0x1
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#define UART_SMART_IDLE_EN (0x1 << 0x3)
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#define CM_DLL_CTRL_NO_OVERRIDE 0x0
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#define CM_DLL_READYST 0x4
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#define NUM_OPPS 6
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extern void enable_dmm_clocks(void);
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extern void enable_emif_clocks(void);
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extern const struct dpll_params dpll_core_opp100;
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extern struct dpll_params dpll_mpu_opp100;
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#endif /* endif _CLOCKS_AM33XX_H_ */
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