mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 19:26:16 +09:00
a47a12becf
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
231 lines
6.5 KiB
C
231 lines
6.5 KiB
C
/*
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* Copyright 2004 Freescale Semiconductor.
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* Copyright (C) 2003 Motorola Inc.
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* Xianghua Xiao (x.xiao@motorola.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* PCI Configuration space access support for MPC85xx PCI Bridge
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*/
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#include <common.h>
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#include <asm/cpm_85xx.h>
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#include <pci.h>
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#if !defined(CONFIG_FSL_PCI_INIT)
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#ifndef CONFIG_SYS_PCI1_MEM_BUS
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#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE
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#endif
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#ifndef CONFIG_SYS_PCI1_IO_BUS
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#define CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_BASE
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#endif
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#ifndef CONFIG_SYS_PCI2_MEM_BUS
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#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI2_MEM_BASE
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#endif
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#ifndef CONFIG_SYS_PCI2_IO_BUS
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#define CONFIG_SYS_PCI2_IO_BUS CONFIG_SYS_PCI2_IO_BASE
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#endif
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static struct pci_controller *pci_hose;
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void
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pci_mpc85xx_init(struct pci_controller *board_hose)
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{
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u16 reg16;
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u32 dev;
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volatile ccsr_pcix_t *pcix = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
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#ifdef CONFIG_MPC85XX_PCI2
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volatile ccsr_pcix_t *pcix2 = (void *)(CONFIG_SYS_MPC85xx_PCIX2_ADDR);
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#endif
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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struct pci_controller * hose;
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pci_hose = board_hose;
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hose = &pci_hose[0];
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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pci_setup_indirect(hose,
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(CONFIG_SYS_IMMR+0x8000),
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(CONFIG_SYS_IMMR+0x8004));
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/*
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* Hose scan.
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*/
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dev = PCI_BDF(hose->first_busno, 0, 0);
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pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
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/* PCI-X init */
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if (CONFIG_SYS_CLK_FREQ < 66000000)
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printf("PCI-X will only work at 66 MHz\n");
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reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
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| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
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pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
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}
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pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BUS >> 12) & 0x000fffff;
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pcix->potear1 = 0x00000000;
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pcix->powbar1 = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff;
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pcix->powbear1 = 0x00000000;
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pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
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POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1));
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pcix->potar2 = (CONFIG_SYS_PCI1_IO_BUS >> 12) & 0x000fffff;
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pcix->potear2 = 0x00000000;
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pcix->powbar2 = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff;
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pcix->powbear2 = 0x00000000;
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pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
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POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI1_IO_SIZE) - 1));
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pcix->pitar1 = 0x00000000;
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pcix->piwbar1 = 0x00000000;
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pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
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PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
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pcix->powar3 = 0;
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pcix->powar4 = 0;
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pcix->piwar2 = 0;
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pcix->piwar3 = 0;
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pci_set_region(hose->regions + 0,
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CONFIG_SYS_PCI1_MEM_BUS,
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CONFIG_SYS_PCI1_MEM_PHYS,
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CONFIG_SYS_PCI1_MEM_SIZE,
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PCI_REGION_MEM);
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pci_set_region(hose->regions + 1,
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CONFIG_SYS_PCI1_IO_BUS,
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CONFIG_SYS_PCI1_IO_PHYS,
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CONFIG_SYS_PCI1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 2;
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pci_register_hose(hose);
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#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
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/*
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* This is a SW workaround for an apparent HW problem
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* in the PCI controller on the MPC85555/41 CDS boards.
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* The first config cycle must be to a valid, known
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* device on the PCI bus in order to trick the PCI
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* controller state machine into a known valid state.
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* Without this, the first config cycle has the chance
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* of hanging the controller permanently, just leaving
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* it in a semi-working state, or leaving it working.
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*
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* Pick on the Tundra, Device 17, to get it right.
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*/
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{
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u8 header_type;
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pci_hose_read_config_byte(hose,
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PCI_BDF(0,BRIDGE_ID,0),
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PCI_HEADER_TYPE,
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&header_type);
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}
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#endif
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hose->last_busno = pci_hose_scan(hose);
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#ifdef CONFIG_MPC85XX_PCI2
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hose = &pci_hose[1];
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hose->first_busno = pci_hose[0].last_busno + 1;
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hose->last_busno = 0xff;
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pci_setup_indirect(hose,
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(CONFIG_SYS_IMMR+0x9000),
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(CONFIG_SYS_IMMR+0x9004));
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dev = PCI_BDF(hose->first_busno, 0, 0);
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pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
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pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BUS >> 12) & 0x000fffff;
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pcix2->potear1 = 0x00000000;
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pcix2->powbar1 = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff;
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pcix2->powbear1 = 0x00000000;
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pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
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POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1));
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pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BUS >> 12) & 0x000fffff;
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pcix2->potear2 = 0x00000000;
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pcix2->powbar2 = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff;
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pcix2->powbear2 = 0x00000000;
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pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
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POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI2_IO_SIZE) - 1));
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pcix2->pitar1 = 0x00000000;
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pcix2->piwbar1 = 0x00000000;
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pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
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PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
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pcix2->powar3 = 0;
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pcix2->powar4 = 0;
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pcix2->piwar2 = 0;
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pcix2->piwar3 = 0;
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pci_set_region(hose->regions + 0,
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CONFIG_SYS_PCI2_MEM_BUS,
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CONFIG_SYS_PCI2_MEM_PHYS,
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CONFIG_SYS_PCI2_MEM_SIZE,
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PCI_REGION_MEM);
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pci_set_region(hose->regions + 1,
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CONFIG_SYS_PCI2_IO_BUS,
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CONFIG_SYS_PCI2_IO_PHYS,
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CONFIG_SYS_PCI2_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 2;
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/*
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* Hose scan.
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*/
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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#endif
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}
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#endif /* !CONFIG_FSL_PCI_INIT */
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