mirror of
https://github.com/brain-hackers/u-boot-brain
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db5741f7a8
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
102 lines
2.9 KiB
C
102 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
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*
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/system_manager.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Configure all the pin muxes
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*/
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void sysmgr_pinmux_init(void)
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{
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populate_sysmgr_pinmux();
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populate_sysmgr_fpgaintf_module();
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}
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/*
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* Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
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* The value is not wrote to SYSMGR.FPGAINTF.MODULE but
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* CONFIG_SYSMGR_ISWGRP_HANDOFF.
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*/
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void populate_sysmgr_fpgaintf_module(void)
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{
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u32 handoff_val = 0;
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/* Enable the signal for those HPS peripherals that use FPGA. */
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if (readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_NAND_USEFPGA) ==
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SYSMGR_FPGAINTF_USEFPGA)
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handoff_val |= SYSMGR_FPGAINTF_NAND;
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if (readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_SDMMC_USEFPGA) ==
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SYSMGR_FPGAINTF_USEFPGA)
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handoff_val |= SYSMGR_FPGAINTF_SDMMC;
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if (readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_SPIM0_USEFPGA) ==
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SYSMGR_FPGAINTF_USEFPGA)
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handoff_val |= SYSMGR_FPGAINTF_SPIM0;
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if (readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_SPIM1_USEFPGA) ==
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SYSMGR_FPGAINTF_USEFPGA)
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handoff_val |= SYSMGR_FPGAINTF_SPIM1;
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writel(handoff_val,
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socfpga_get_sysmgr_addr() + SYSMGR_S10_FPGAINTF_EN2);
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handoff_val = 0;
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if (readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_EMAC0_USEFPGA) ==
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SYSMGR_FPGAINTF_USEFPGA)
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handoff_val |= SYSMGR_FPGAINTF_EMAC0;
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if (readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_EMAC1_USEFPGA) ==
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SYSMGR_FPGAINTF_USEFPGA)
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handoff_val |= SYSMGR_FPGAINTF_EMAC1;
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if (readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_EMAC2_USEFPGA) ==
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SYSMGR_FPGAINTF_USEFPGA)
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handoff_val |= SYSMGR_FPGAINTF_EMAC2;
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writel(handoff_val,
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socfpga_get_sysmgr_addr() + SYSMGR_S10_FPGAINTF_EN3);
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}
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/*
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* Configure all the pin muxes
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*/
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void populate_sysmgr_pinmux(void)
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{
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const u32 *sys_mgr_table_u32;
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unsigned int len, i;
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/* setup the pin sel */
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sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len);
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for (i = 0; i < len; i = i + 2) {
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writel(sys_mgr_table_u32[i + 1],
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sys_mgr_table_u32[i] +
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(u8 *)socfpga_get_sysmgr_addr() + SYSMGR_S10_PINSEL0);
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}
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/* setup the pin ctrl */
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sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len);
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for (i = 0; i < len; i = i + 2) {
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writel(sys_mgr_table_u32[i + 1],
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sys_mgr_table_u32[i] +
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(u8 *)socfpga_get_sysmgr_addr() + SYSMGR_S10_IOCTRL0);
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}
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/* setup the fpga use */
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sysmgr_pinmux_table_fpga(&sys_mgr_table_u32, &len);
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for (i = 0; i < len; i = i + 2) {
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writel(sys_mgr_table_u32[i + 1],
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sys_mgr_table_u32[i] +
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(u8 *)socfpga_get_sysmgr_addr() +
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SYSMGR_S10_EMAC0_USEFPGA);
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}
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/* setup the IO delay */
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sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len);
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for (i = 0; i < len; i = i + 2) {
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writel(sys_mgr_table_u32[i + 1],
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sys_mgr_table_u32[i] +
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(u8 *)socfpga_get_sysmgr_addr() + SYSMGR_S10_IODELAY0);
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}
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}
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