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https://github.com/brain-hackers/u-boot-brain
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db5741f7a8
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
106 lines
2.9 KiB
C
106 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
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*
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/system_manager.h>
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#include <dt-bindings/reset/altr,rst-mgr-s10.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Assert or de-assert SoCFPGA reset manager reset. */
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void socfpga_per_reset(u32 reset, int set)
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{
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unsigned long reg;
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if (RSTMGR_BANK(reset) == 0)
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reg = RSTMGR_S10_MPUMODRST;
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else if (RSTMGR_BANK(reset) == 1)
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reg = RSTMGR_S10_PER0MODRST;
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else if (RSTMGR_BANK(reset) == 2)
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reg = RSTMGR_S10_PER1MODRST;
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else if (RSTMGR_BANK(reset) == 3)
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reg = RSTMGR_S10_BRGMODRST;
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else /* Invalid reset register, do nothing */
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return;
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if (set)
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setbits_le32(socfpga_get_rstmgr_addr() + reg,
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1 << RSTMGR_RESET(reset));
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else
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clrbits_le32(socfpga_get_rstmgr_addr() + reg,
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1 << RSTMGR_RESET(reset));
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}
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/*
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* Assert reset on every peripheral but L4WD0.
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* Watchdog must be kept intact to prevent glitches
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* and/or hangs.
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*/
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void socfpga_per_reset_all(void)
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{
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const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
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/* disable all except OCP and l4wd0. OCP disable later */
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writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
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socfpga_get_rstmgr_addr() + RSTMGR_S10_PER0MODRST);
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writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_S10_PER0MODRST);
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writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_S10_PER1MODRST);
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}
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void socfpga_bridges_reset(int enable)
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{
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if (enable) {
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/* clear idle request to all bridges */
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setbits_le32(socfpga_get_sysmgr_addr() +
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SYSMGR_S10_NOC_IDLEREQ_CLR, ~0);
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/* Release all bridges from reset state */
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clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_S10_BRGMODRST,
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~0);
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/* Poll until all idleack to 0 */
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while (readl(socfpga_get_sysmgr_addr() +
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SYSMGR_S10_NOC_IDLEACK))
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;
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} else {
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/* set idle request to all bridges */
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writel(~0,
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socfpga_get_sysmgr_addr() + SYSMGR_S10_NOC_IDLEREQ_SET);
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/* Enable the NOC timeout */
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writel(1, socfpga_get_sysmgr_addr() + SYSMGR_S10_NOC_TIMEOUT);
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/* Poll until all idleack to 1 */
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while ((readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_NOC_IDLEACK) ^
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(SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
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;
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/* Poll until all idlestatus to 1 */
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while ((readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_NOC_IDLESTATUS) ^
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(SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
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;
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/* Reset all bridges (except NOR DDR scheduler & F2S) */
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setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_S10_BRGMODRST,
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~(RSTMGR_BRGMODRST_DDRSCH_MASK |
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RSTMGR_BRGMODRST_FPGA2SOC_MASK));
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/* Disable NOC timeout */
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writel(0, socfpga_get_sysmgr_addr() + SYSMGR_S10_NOC_TIMEOUT);
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}
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}
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/*
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* Return non-zero if the CPU has been warm reset
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*/
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int cpu_has_been_warmreset(void)
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{
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return readl(socfpga_get_rstmgr_addr() + RSTMGR_S10_STATUS) &
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RSTMGR_L4WD_MPU_WARMRESET_MASK;
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}
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