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https://github.com/brain-hackers/u-boot-brain
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25ddd1fb0a
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
443 lines
14 KiB
C
443 lines
14 KiB
C
/*
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* (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
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* (C) Copyright 2009, DAVE Srl <www.dave.eu>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* modifications for the MECP5123 by reinhard.arlt@esd-electronics.com
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*
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*/
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/*
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* MECP5123 board configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_MECP5123 1
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/*
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* Memory map for the MECP5123 board:
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*
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* 0x0000_0000 - 0x1FFF_FFFF DDR RAM (512 MB)
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* 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
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* 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
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* 0x8200_0000 - 0x8200_FFFF VPC-3 (64 KB)
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* 0xFFC0_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
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*/
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 Family */
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#define CONFIG_MPC512X 1 /* MPC512X family */
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#define CONFIG_SYS_TEXT_BASE 0xFFF00000
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#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
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#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
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#define CONFIG_MISC_INIT_R
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#define CONFIG_SYS_IMMR 0x80000000
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#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100)
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
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#define CONFIG_SYS_MEMTEST_END 0x00400000
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/*
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* DDR Setup - manually set all parameters as there's no SPD etc.
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*/
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#define CONFIG_SYS_DDR_SIZE 512 /* MB */
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
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#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036
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/* DDR Controller Configuration
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*
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* SYS_CFG:
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* [31:31] MDDRC Soft Reset: Diabled
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* [30:30] DRAM CKE pin: Enabled
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* [29:29] DRAM CLK: Enabled
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* [28:28] Command Mode: Enabled (For initialization only)
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* [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
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* [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
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* [20:19] Read Test: DON'T USE
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* [18:18] Self Refresh: Enabled
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* [17:17] 16bit Mode: Disabled
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* [16:13] Ready Delay: 2
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* [12:12] Half DQS Delay: Disabled
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* [11:11] Quarter DQS Delay: Disabled
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* [10:08] Write Delay: 2
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* [07:07] Early ODT: Disabled
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* [06:06] On DIE Termination: Disabled
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* [05:05] FIFO Overflow Clear: DON'T USE here
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* [04:04] FIFO Underflow Clear: DON'T USE here
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* [03:03] FIFO Overflow Pending: DON'T USE here
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* [02:02] FIFO Underlfow Pending: DON'T USE here
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* [01:01] FIFO Overlfow Enabled: Enabled
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* [00:00] FIFO Underflow Enabled: Enabled
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* TIME_CFG0
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* [31:16] DRAM Refresh Time: 0 CSB clocks
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* [15:8] DRAM Command Time: 0 CSB clocks
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* [07:00] DRAM Precharge Time: 0 CSB clocks
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* TIME_CFG1
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* [31:26] DRAM tRFC:
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* [25:21] DRAM tWR1:
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* [20:17] DRAM tWRT1:
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* [16:11] DRAM tDRR:
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* [10:05] DRAM tRC:
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* [04:00] DRAM tRAS:
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* TIME_CFG2
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* [31:28] DRAM tRCD:
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* [27:23] DRAM tFAW:
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* [22:19] DRAM tRTW1:
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* [18:15] DRAM tCCD:
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* [14:10] DRAM tRTP:
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* [09:05] DRAM tRP:
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* [04:00] DRAM tRPA
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*/
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#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00
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#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E
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#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
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#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
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#define CONFIG_SYS_DDRCMD_NOP 0x01380000
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#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
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#define CONFIG_SYS_DDRCMD_EM2 0x01020000
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#define CONFIG_SYS_DDRCMD_EM3 0x01030000
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#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000
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#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
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#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
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#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x01010780
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/* DDR Priority Manager Configuration */
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#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
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#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
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#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
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#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
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#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
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#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
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#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
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#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
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#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
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#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
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#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
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#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
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#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
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#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
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#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
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#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
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#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
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#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
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#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
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#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
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#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
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#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
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#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
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/*
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* NOR FLASH on the Local Bus
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*/
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#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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#define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of FLASH */
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#define CONFIG_SYS_FLASH_SIZE 0x00400000 /* max flash size */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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/*
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* NAND FLASH
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* drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
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*/
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#define CONFIG_CMD_NAND
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#define CONFIG_NAND_MPC5121_NFC
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
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/*
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* Configuration parameters for MPC5121 NAND driver
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*/
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#define CONFIG_FSL_NFC_WIDTH 1
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#define CONFIG_FSL_NFC_WRITE_SIZE 2048
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#define CONFIG_FSL_NFC_SPARE_SIZE 64
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#define CONFIG_FSL_NFC_CHIPS 1
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#define CONFIG_SYS_SRAM_BASE 0x30000000
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#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
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/* ALE active low, data size 4bytes */
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#define CONFIG_SYS_CS0_CFG 0x05051150
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/* Use not alternative CS timing */
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#define CONFIG_SYS_CS_ALETIMING 0x00000000
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/* ALE active low, data size 4bytes */
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#define CONFIG_SYS_CS1_CFG 0x1f1f3090
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#define CONFIG_SYS_VPC3_BASE 0x82000000 /* start of VPC3 space */
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#define CONFIG_SYS_VPC3_SIZE 0x00010000 /* max VPC3 size */
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/* Use SRAM for initial stack */
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Init RAM addr */
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#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Monitor length */
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#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Malloc size */
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
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#if CONFIG_PSC_CONSOLE != 3
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#error CONFIG_PSC_CONSOLE must be 3
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#endif
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#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
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#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
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#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
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#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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/* Use the HUSH parser */
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#define CONFIG_SYS_HUSH_PARSER
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#endif
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/* I2C */
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
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#define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */
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/*
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* IIM - IC Identification Module
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*/
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#undef CONFIG_IIM
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/*
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* EEPROM configuration
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*/
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
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#define CONFIG_SYS_EEPROM_WREN /* Use EEPROM write protect */
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC512x_FEC 1
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#define CONFIG_NET_MULTI
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#define CONFIG_PHY_ADDR 0x1
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_FEC_AN_TIMEOUT 1
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#define CONFIG_HAS_ETH0
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/*
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* Configure on-board RTC
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*/
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#define CONFIG_SYS_RTC_BUS_NUM 0x01
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#define CONFIG_SYS_I2C_RTC_ADDR 0x32
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#define CONFIG_RTC_RX8025
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/*
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* Environment
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*/
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#define CONFIG_ENV_IS_IN_EEPROM /* Store env in I2C EEPROM */
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#define CONFIG_ENV_SIZE 0x1000
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#define CONFIG_ENV_OFFSET 0x0000 /* environment starts here */
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#define CONFIG_LOADS_ECHO /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_DATE
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#undef CONFIG_CMD_FUSE
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#undef CONFIG_CMD_IDE
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#undef CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_ELF
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#define CONFIG_DOS_PARTITION
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/*
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* Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
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* For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
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* to 0xFFFF, watchdog timeouts after about 64s. For details refer
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* to chapter 36 of the MPC5121e Reference Manual.
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*/
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/* #define CONFIG_WATCHDOG */ /* enable watchdog */
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#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#ifdef CONFIG_CMD_KGDB
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# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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/* max number of command args */
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#define CONFIG_SYS_MAXARGS 32
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_HZ 1000
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 256 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Linux initial memory map */
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/* Cache Configuration */
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#define CONFIG_SYS_DCACHE_SIZE 32768
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#ifdef CONFIG_CMD_KGDB
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#define CONFIG_SYS_CACHELINE_SHIFT 5
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#endif
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#define CONFIG_SYS_HID0_INIT 0x000000000
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#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
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#define CONFIG_SYS_HID2 HID2_HBE
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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#ifdef CONFIG_CMD_KGDB
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Environment Configuration
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*/
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#define CONFIG_TIMESTAMP
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#define CONFIG_HOSTNAME mecp512x
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#define CONFIG_BOOTFILE /tftpboot/mecp512x/uImage
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#define CONFIG_ROOTPATH /tftpboot/mecp512x/target_root
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#define CONFIG_LOADADDR 400000 /* def. location for tftp and bootm */
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#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
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#define CONFIG_PREBOOT "echo;" \
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"echo Welcome to MECP5123" \
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"echo"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"u-boot_addr_r=200000\0" \
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"kernel_addr_r=600000\0" \
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"fdt_addr_r=880000\0" \
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"ramdisk_addr_r=900000\0" \
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"u-boot_addr=FFF00000\0" \
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"kernel_addr=FFC40000\0" \
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"fdt_addr=FFEC0000\0" \
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"ramdisk_addr=FC040000\0" \
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"ramdiskfile=/tftpboot/mecp512x/uRamdisk\0" \
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"u-boot=/tftpboot/mecp512x/u-boot.bin\0" \
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"bootfile=/tftpboot/mecp512x/uImage\0" \
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"fdtfile=/tftpboot/mecp512x/mecp512x.dtb\0" \
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"rootpath=/tftpboot/mecp512x/target_root\n" \
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"netdev=eth0\0" \
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"consdev=ttyPSC0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} " \
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"console=${consdev},${baudrate}\0" \
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"flash_nfs=run nfsargs addip addtty;" \
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"bootm ${kernel_addr} - ${fdt_addr}\0" \
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"flash_self=run ramargs addip addtty;" \
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"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
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"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
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"tftp ${fdt_addr_r} ${fdtfile};" \
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"run nfsargs addip addtty;" \
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"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
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"net_self=tftp ${kernel_addr_r} ${bootfile};" \
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"tftp ${ramdisk_addr_r} ${ramdiskfile};" \
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"tftp ${fdt_addr_r} ${fdtfile};" \
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"run ramargs addip addtty;" \
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"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
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"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
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|
"update=protect off ${u-boot_addr} +${filesize};" \
|
|
"era ${u-boot_addr} +${filesize};" \
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|
"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
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|
"upd=run load update\0" \
|
|
""
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|
|
|
#define CONFIG_BOOTCOMMAND "run flash_self"
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|
|
|
#define CONFIG_OF_LIBFDT
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|
#define CONFIG_OF_BOARD_SETUP
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|
|
|
#define OF_CPU "PowerPC,5121@0"
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|
#define OF_SOC_COMPAT "fsl,mpc5121-immr"
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|
#define OF_TBCLK (bd->bi_busfreq / 4)
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|
#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
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|
|
|
#endif /* __CONFIG_H */
|