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https://github.com/brain-hackers/u-boot-brain
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7659ea32a6
This patch adds device tree and driver model watchdog support, converts the legacy omap watchdog driver to driver model for TI AM335x chipsets. The following compile warning is removed: ===================== WARNING ====================== This board does not use CONFIG_WDT (DM watchdog support). Please update the board to use CONFIG_WDT before the v2019.10 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ==================================================== CONFIG_HW_WATCHDOG is no more a default option for AM33XX devices after DT/DM conversion, adjusted kconfig accordingly. DM watchdog support is enabled by default in SPL. The SPL image doesn't fit into SRAM because of size constraints and build breaks with an overflow. For this reason DM watchdog support should be disabled in SPL, driver code should be adjusted accordingly to serve this purpose. Built and tested on AM335x device (BeagleboneBlack), compile tested for all other AM33xx based boards. Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
65 lines
1.8 KiB
C
65 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* omap_wdt.h
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*
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* OMAP Watchdog header file
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*/
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#ifndef __OMAP_WDT_H__
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#define __OMAP_WDT_H__
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/*
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* Watchdog:
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* Using the prescaler, the OMAP watchdog could go for many
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* months before firing. These limits work without scaling,
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* with the 60 second default assumed by most tools and docs.
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*/
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#define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */
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#define TIMER_MARGIN_DEFAULT 60 /* 60 secs */
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#define TIMER_MARGIN_MIN 1
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#define PTV 0 /* prescale */
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#define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
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#define WDT_WWPS_PEND_WCLR BIT(0)
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#define WDT_WWPS_PEND_WLDR BIT(2)
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#define WDT_WWPS_PEND_WTGR BIT(3)
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#define WDT_WWPS_PEND_WSPR BIT(4)
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#define WDT_WCLR_PRE BIT(5)
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#define WDT_WCLR_PTV_OFF 2
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/* Watchdog timer registers */
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struct wd_timer {
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unsigned int resv1[4];
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unsigned int wdtwdsc; /* offset 0x010 */
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unsigned int wdtwdst; /* offset 0x014 */
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unsigned int wdtwisr; /* offset 0x018 */
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unsigned int wdtwier; /* offset 0x01C */
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unsigned int wdtwwer; /* offset 0x020 */
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unsigned int wdtwclr; /* offset 0x024 */
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unsigned int wdtwcrr; /* offset 0x028 */
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unsigned int wdtwldr; /* offset 0x02C */
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unsigned int wdtwtgr; /* offset 0x030 */
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unsigned int wdtwwps; /* offset 0x034 */
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unsigned int resv2[3];
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unsigned int wdtwdly; /* offset 0x044 */
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unsigned int wdtwspr; /* offset 0x048 */
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unsigned int resv3[1];
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unsigned int wdtwqeoi; /* offset 0x050 */
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unsigned int wdtwqstar; /* offset 0x054 */
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unsigned int wdtwqsta; /* offset 0x058 */
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unsigned int wdtwqens; /* offset 0x05C */
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unsigned int wdtwqenc; /* offset 0x060 */
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unsigned int resv4[39];
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unsigned int wdt_unfr; /* offset 0x100 */
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};
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struct omap3_wdt_priv {
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struct wd_timer *regs;
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unsigned int wdt_trgr_pattern;
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};
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#endif /* __OMAP_WDT_H__ */
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