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![]() The board has both VDD_SOC_IN and VDD_ARM_IN rails connected to the same PMIC rail, align the LDO voltages to avoid leaking inside the MX6SX SoC. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Stefano Babic <sbabic@denx.de> |
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vining_2000 | ||
vining_fpga |