100 lines
1.9 KiB
C
100 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Intel Corporation <www.intel.com>
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*
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*/
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#include <asm/io.h>
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#include <asm/u-boot.h>
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#include <asm/utils.h>
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#include <common.h>
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#include <hang.h>
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#include <image.h>
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#include <spl.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/firewall.h>
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#include <asm/arch/mailbox_s10.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/system_manager.h>
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#include <watchdog.h>
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#include <dm/uclass.h>
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DECLARE_GLOBAL_DATA_PTR;
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_MMC1;
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}
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#ifdef CONFIG_SPL_MMC_SUPPORT
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u32 spl_boot_mode(const u32 boot_device)
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{
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#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
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return MMCSD_MODE_FS;
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#else
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return MMCSD_MODE_RAW;
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#endif
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}
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#endif
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void board_init_f(ulong dummy)
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{
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int ret;
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struct udevice *dev;
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ret = spl_early_init();
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if (ret)
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hang();
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socfpga_get_managers_addr();
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#ifdef CONFIG_HW_WATCHDOG
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/* Ensure watchdog is paused when debugging is happening */
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writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
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socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
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/* Enable watchdog before initializing the HW */
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socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
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socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
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hw_watchdog_init();
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#endif
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/* ensure all processors are not released prior Linux boot */
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writeq(0, CPU_RELEASE_ADDR);
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timer_init();
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sysmgr_pinmux_init();
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ret = uclass_get_device(UCLASS_CLK, 0, &dev);
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if (ret) {
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debug("Clock init failed: %d\n", ret);
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hang();
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}
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preloader_console_init();
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cm_print_clock_quick_summary();
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firewall_setup();
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ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
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if (ret) {
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debug("CCU init failed: %d\n", ret);
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hang();
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}
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#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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debug("DRAM init failed: %d\n", ret);
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hang();
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}
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#endif
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mbox_init();
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#ifdef CONFIG_CADENCE_QSPI
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mbox_qspi_open();
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#endif
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}
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