mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
398 lines
12 KiB
C
398 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Keystone2: Common SoC definitions, structures etc.
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include <config.h>
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#ifndef __ASSEMBLY__
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#include <linux/sizes.h>
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#include <asm/io.h>
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#define REG(addr) (*(volatile unsigned int *)(addr))
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#define REG_P(addr) ((volatile unsigned int *)(addr))
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typedef volatile unsigned int dv_reg;
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typedef volatile unsigned int *dv_reg_p;
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#endif
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#define KS2_DDRPHY_PIR_OFFSET 0x04
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#define KS2_DDRPHY_PGCR0_OFFSET 0x08
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#define KS2_DDRPHY_PGCR1_OFFSET 0x0C
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#define KS2_DDRPHY_PGSR0_OFFSET 0x10
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#define KS2_DDRPHY_PGSR1_OFFSET 0x14
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#define KS2_DDRPHY_PLLCR_OFFSET 0x18
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#define KS2_DDRPHY_PTR0_OFFSET 0x1C
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#define KS2_DDRPHY_PTR1_OFFSET 0x20
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#define KS2_DDRPHY_PTR2_OFFSET 0x24
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#define KS2_DDRPHY_PTR3_OFFSET 0x28
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#define KS2_DDRPHY_PTR4_OFFSET 0x2C
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#define KS2_DDRPHY_DCR_OFFSET 0x44
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#define KS2_DDRPHY_DTPR0_OFFSET 0x48
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#define KS2_DDRPHY_DTPR1_OFFSET 0x4C
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#define KS2_DDRPHY_DTPR2_OFFSET 0x50
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#define KS2_DDRPHY_MR0_OFFSET 0x54
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#define KS2_DDRPHY_MR1_OFFSET 0x58
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#define KS2_DDRPHY_MR2_OFFSET 0x5C
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#define KS2_DDRPHY_DTCR_OFFSET 0x68
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#define KS2_DDRPHY_PGCR2_OFFSET 0x8C
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#define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184
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#define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194
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#define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4
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#define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4
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#define KS2_DDRPHY_DATX8_2_OFFSET 0x240
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#define KS2_DDRPHY_DATX8_3_OFFSET 0x280
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#define KS2_DDRPHY_DATX8_4_OFFSET 0x2C0
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#define KS2_DDRPHY_DATX8_5_OFFSET 0x300
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#define KS2_DDRPHY_DATX8_6_OFFSET 0x340
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#define KS2_DDRPHY_DATX8_7_OFFSET 0x380
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#define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0
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#define IODDRM_MASK 0x00000180
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#define ZCKSEL_MASK 0x01800000
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#define CL_MASK 0x00000072
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#define WR_MASK 0x00000E00
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#define BL_MASK 0x00000003
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#define RRMODE_MASK 0x00040000
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#define UDIMM_MASK 0x20000000
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#define BYTEMASK_MASK 0x0003FC00
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#define MPRDQ_MASK 0x00000080
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#define PDQ_MASK 0x00000070
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#define NOSRA_MASK 0x08000000
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#define ECC_MASK 0x00000001
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#define DXEN_MASK 0x00000001
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/* DDR3 definitions */
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#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000
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#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000
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#define KS2_DDR3A_DDRPHYC 0x02329000
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#define EMIF1_BASE KS2_DDR3A_EMIF_CTRL_BASE
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#define KS2_DDR3_MIDR_OFFSET 0x00
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#define KS2_DDR3_STATUS_OFFSET 0x04
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#define KS2_DDR3_SDCFG_OFFSET 0x08
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#define KS2_DDR3_SDRFC_OFFSET 0x10
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#define KS2_DDR3_SDTIM1_OFFSET 0x18
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#define KS2_DDR3_SDTIM2_OFFSET 0x1C
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#define KS2_DDR3_SDTIM3_OFFSET 0x20
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#define KS2_DDR3_SDTIM4_OFFSET 0x28
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#define KS2_DDR3_PMCTL_OFFSET 0x38
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#define KS2_DDR3_ZQCFG_OFFSET 0xC8
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#define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000
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/* DDR3 ECC */
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#define KS2_DDR3_ECC_INT_STATUS_OFFSET 0x0AC
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#define KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET 0x0B4
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#define KS2_DDR3_ECC_CTRL_OFFSET 0x110
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#define KS2_DDR3_ECC_ADDR_RANGE1_OFFSET 0x114
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#define KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET 0x130
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#define KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET 0x13C
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/* DDR3 ECC Interrupt Status register */
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#define KS2_DDR3_1B_ECC_ERR_SYS BIT(5)
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#define KS2_DDR3_2B_ECC_ERR_SYS BIT(4)
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#define KS2_DDR3_WR_ECC_ERR_SYS BIT(3)
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/* DDR3 ECC Control register */
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#define KS2_DDR3_ECC_EN BIT(31)
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#define KS2_DDR3_ECC_ADDR_RNG_PROT BIT(30)
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#define KS2_DDR3_ECC_VERIFY_EN BIT(29)
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#define KS2_DDR3_ECC_RMW_EN BIT(28)
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#define KS2_DDR3_ECC_ADDR_RNG_1_EN BIT(0)
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#define KS2_DDR3_ECC_ENABLE (KS2_DDR3_ECC_EN | \
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KS2_DDR3_ECC_ADDR_RNG_PROT | \
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KS2_DDR3_ECC_VERIFY_EN)
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/* EDMA */
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#define KS2_EDMA0_BASE 0x02700000
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/* EDMA3 register offsets */
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#define KS2_EDMA_QCHMAP0 0x0200
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#define KS2_EDMA_IPR 0x1068
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#define KS2_EDMA_ICR 0x1070
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#define KS2_EDMA_QEECR 0x1088
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#define KS2_EDMA_QEESR 0x108c
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#define KS2_EDMA_PARAM_1(x) (0x4020 + (4 * x))
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/* NETCP pktdma */
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#ifdef CONFIG_SOC_K2G
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#define KS2_NETCP_PDMA_RX_FREE_QUEUE 113
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#define KS2_NETCP_PDMA_RX_RCV_QUEUE 114
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#else
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#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001
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#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002
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#endif
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/* Chip Interrupt Controller */
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#define KS2_CIC2_BASE 0x02608000
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/* Chip Interrupt Controller register offsets */
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#define KS2_CIC_CTRL 0x04
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#define KS2_CIC_HOST_CTRL 0x0C
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#define KS2_CIC_GLOBAL_ENABLE 0x10
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#define KS2_CIC_SYS_ENABLE_IDX_SET 0x28
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#define KS2_CIC_HOST_ENABLE_IDX_SET 0x34
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#define KS2_CIC_CHAN_MAP(n) (0x0400 + (n << 2))
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#define KS2_UART0_BASE 0x02530c00
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#define KS2_UART1_BASE 0x02531000
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/* Boot Config */
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#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
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#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
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#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
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#define KS2_DEVCFG (KS2_DEVICE_STATE_CTRL_BASE + 0x14c)
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#define KS2_ETHERNET_CFG (KS2_DEVICE_STATE_CTRL_BASE + 0xe20)
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#define KS2_ETHERNET_RGMII 2
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/* PSC */
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#define KS2_PSC_BASE 0x02350000
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#define KS2_LPSC_GEM_0 15
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#define KS2_LPSC_TETRIS 52
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#define KS2_TETRIS_PWR_DOMAIN 31
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#define KS2_GEM_0_PWR_DOMAIN 8
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/* Chip configuration unlock codes and registers */
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#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
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#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
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#define KS2_KICK0_MAGIC 0x83e70b13
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#define KS2_KICK1_MAGIC 0x95a4f1e0
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/* PLL control registers */
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#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
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#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
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#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
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#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
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#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
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#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
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#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
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#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
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#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
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#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
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#define KS2_UARTPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x390)
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#define KS2_UARTPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x394)
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#define KS2_PLL_CNTRL_BASE 0x02310000
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#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE
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#define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4)
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#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8)
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#define KS2_RSTCTRL_RSCFG (KS2_PLL_CNTRL_BASE + 0xec)
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#define KS2_RSTCTRL_KEY 0x5a69
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#define KS2_RSTCTRL_MASK 0xffff0000
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#define KS2_RSTCTRL_SWRST 0xfffe0000
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#define KS2_RSTYPE_PLL_SOFT BIT(13)
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/* SPI */
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#ifdef CONFIG_SOC_K2G
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#define KS2_SPI0_BASE 0x21805400
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#define KS2_SPI1_BASE 0x21805800
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#define KS2_SPI2_BASE 0x21805c00
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#define KS2_SPI3_BASE 0x21806000
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#else
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#define KS2_SPI0_BASE 0x21000400
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#define KS2_SPI1_BASE 0x21000600
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#define KS2_SPI2_BASE 0x21000800
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#define KS2_SPI_BASE KS2_SPI0_BASE
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#endif
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/* AEMIF */
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#define KS2_AEMIF_CNTRL_BASE 0x21000a00
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#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
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/* Flag from ks2_debug options to check if DSPs need to stay ON */
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#define DBG_LEAVE_DSPS_ON 0x1
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/* MSMC control */
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#define KS2_MSMC_CTRL_BASE 0x0bc00000
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#define KS2_MSMC_DATA_BASE 0x0c000000
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/* KS2 Generic Privilege ID Settings for MSMC2 */
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#define KS2_MSMC_SEGMENT_C6X_0 0
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#define KS2_MSMC_SEGMENT_C6X_1 1
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#define KS2_MSMC_SEGMENT_C6X_2 2
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#define KS2_MSMC_SEGMENT_C6X_3 3
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#define KS2_MSMC_SEGMENT_C6X_4 4
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#define KS2_MSMC_SEGMENT_C6X_5 5
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#define KS2_MSMC_SEGMENT_C6X_6 6
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#define KS2_MSMC_SEGMENT_C6X_7 7
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#define KS2_MSMC_SEGMENT_DEBUG 12
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/* KS2 HK/L/E MSMC PRIVIDs for MSMC2 */
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#define K2HKLE_MSMC_SEGMENT_ARM 8
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#define K2HKLE_MSMC_SEGMENT_NETCP 9
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#define K2HKLE_MSMC_SEGMENT_QM_PDSP 10
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#define K2HKLE_MSMC_SEGMENT_PCIE0 11
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/* K2HK specific Privilege ID Settings */
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#define K2HKE_MSMC_SEGMENT_HYPERLINK 14
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/* K2L specific Privilege ID Settings */
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#define K2L_MSMC_SEGMENT_PCIE1 14
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/* K2E specific Privilege ID Settings */
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#define K2E_MSMC_SEGMENT_PCIE1 13
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#define K2E_MSMC_SEGMENT_TSIP 15
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/* K2G specific Privilege ID Settings */
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#define K2G_MSMC_SEGMENT_ARM 1
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#define K2G_MSMC_SEGMENT_ICSS0 2
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#define K2G_MSMC_SEGMENT_ICSS1 3
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#define K2G_MSMC_SEGMENT_NSS 4
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#define K2G_MSMC_SEGMENT_PCIE 5
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#define K2G_MSMC_SEGMENT_USB 6
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#define K2G_MSMC_SEGMENT_MLB 8
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#define K2G_MSMC_SEGMENT_PMMC 9
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#define K2G_MSMC_SEGMENT_DSS 10
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#define K2G_MSMC_SEGMENT_MMC 11
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/* MSMC segment size shift bits */
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#define KS2_MSMC_SEG_SIZE_SHIFT 12
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#define KS2_MSMC_MAP_SEG_NUM (2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT))
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#define KS2_MSMC_DST_SEG_BASE (CONFIG_SYS_LPAE_SDRAM_BASE >> \
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KS2_MSMC_SEG_SIZE_SHIFT)
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/* Device speed */
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#define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
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#define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
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#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
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/* Queue manager */
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#ifdef CONFIG_SOC_K2G
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#define KS2_QM_BASE_ADDRESS 0x040C0000
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#define KS2_QM_CONF_BASE 0x04040000
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#define KS2_QM_DESC_SETUP_BASE 0x04080000
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#define KS2_QM_STATUS_RAM_BASE 0x0 /* K2G doesn't have it */
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#define KS2_QM_INTD_CONF_BASE 0x0
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#define KS2_QM_PDSP1_CMD_BASE 0x0
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#define KS2_QM_PDSP1_CTRL_BASE 0x0
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#define KS2_QM_PDSP1_IRAM_BASE 0x0
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#define KS2_QM_MANAGER_QUEUES_BASE 0x040c0000
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#define KS2_QM_MANAGER_Q_PROXY_BASE 0x04040200
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#define KS2_QM_QUEUE_STATUS_BASE 0x04100000
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#define KS2_QM_LINK_RAM_BASE 0x04020000
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#define KS2_QM_REGION_NUM 8
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#define KS2_QM_QPOOL_NUM 112
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#else
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#define KS2_QM_BASE_ADDRESS 0x23a80000
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#define KS2_QM_CONF_BASE 0x02a02000
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#define KS2_QM_DESC_SETUP_BASE 0x02a03000
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#define KS2_QM_STATUS_RAM_BASE 0x02a06000
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#define KS2_QM_INTD_CONF_BASE 0x02a0c000
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#define KS2_QM_PDSP1_CMD_BASE 0x02a20000
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#define KS2_QM_PDSP1_CTRL_BASE 0x02a0f000
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#define KS2_QM_PDSP1_IRAM_BASE 0x02a10000
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#define KS2_QM_MANAGER_QUEUES_BASE 0x02a80000
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#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
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#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000
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#define KS2_QM_LINK_RAM_BASE 0x00100000
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#define KS2_QM_REGION_NUM 64
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#define KS2_QM_QPOOL_NUM 4000
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#endif
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/* USB */
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#define KS2_USB_SS_BASE 0x02680000
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#define KS2_USB_HOST_XHCI_BASE (KS2_USB_SS_BASE + 0x10000)
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#define KS2_DEV_USB_PHY_BASE 0x02620738
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#define KS2_USB_PHY_CFG_BASE 0x02630000
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#define KS2_MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
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/* SGMII SerDes */
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#define KS2_SGMII_SERDES_BASE 0x0232a000
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/* JTAG ID register */
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#define JTAGID_VARIANT_SHIFT 28
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#define JTAGID_VARIANT_MASK (0xf << 28)
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#define JTAGID_PART_NUM_SHIFT 12
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#define JTAGID_PART_NUM_MASK (0xffff << 12)
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/* PART NUMBER definitions */
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#define CPU_66AK2Hx 0xb981
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#define CPU_66AK2Ex 0xb9a6
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#define CPU_66AK2Lx 0xb9a7
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#define CPU_66AK2Gx 0xbb06
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/* Variant definitions */
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#define CPU_66AK2G1x 0x08
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/* DEVSPEED register */
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#define DEVSPEED_DEVSPEED_SHIFT 16
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#define DEVSPEED_DEVSPEED_MASK (0xfff << 16)
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#define DEVSPEED_ARMSPEED_SHIFT 0
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#define DEVSPEED_ARMSPEED_MASK 0xfff
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#define DEVSPEED_NUMSPDS 12
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#ifdef CONFIG_SOC_K2HK
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#include <asm/arch/hardware-k2hk.h>
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#endif
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#ifdef CONFIG_SOC_K2E
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#include <asm/arch/hardware-k2e.h>
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#endif
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#ifdef CONFIG_SOC_K2L
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#include <asm/arch/hardware-k2l.h>
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#endif
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#ifdef CONFIG_SOC_K2G
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#include <asm/arch/hardware-k2g.h>
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#endif
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#ifndef __ASSEMBLY__
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static inline u16 get_part_number(void)
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{
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u32 jtag_id = __raw_readl(KS2_JTAG_ID_REG);
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return (jtag_id & JTAGID_PART_NUM_MASK) >> JTAGID_PART_NUM_SHIFT;
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}
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static inline u8 cpu_is_k2hk(void)
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{
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return get_part_number() == CPU_66AK2Hx;
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}
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static inline u8 cpu_is_k2e(void)
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{
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return get_part_number() == CPU_66AK2Ex;
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}
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static inline u8 cpu_is_k2l(void)
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{
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return get_part_number() == CPU_66AK2Lx;
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}
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static inline u8 cpu_is_k2g(void)
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{
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return get_part_number() == CPU_66AK2Gx;
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}
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static inline u8 cpu_revision(void)
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{
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u32 jtag_id = __raw_readl(KS2_JTAG_ID_REG);
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u8 rev = (jtag_id & JTAGID_VARIANT_MASK) >> JTAGID_VARIANT_SHIFT;
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return rev;
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}
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int cpu_to_bus(u32 *ptr, u32 length);
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void sdelay(unsigned long);
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#endif
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#endif /* __ASM_ARCH_HARDWARE_H */
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