mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 03:36:16 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
384 lines
10 KiB
C
384 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Board functions for TI AM335X based draco board
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* (C) Copyright 2013 Siemens Schweiz AG
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* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* Based on:
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*
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* Board functions for TI AM335X based boards
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* u-boot:/board/ti/am335x/board.c
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*/
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#include <common.h>
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#include <errno.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include <watchdog.h>
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#include "board.h"
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#include "../common/factoryset.h"
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#include <nand.h>
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#ifdef CONFIG_SPL_BUILD
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static struct draco_baseboard_id __attribute__((section(".data"))) settings;
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#if DDR_PLL_FREQ == 303
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#if !defined(CONFIG_TARGET_ETAMIN)
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/* Default@303MHz-i0 */
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const struct ddr3_data ddr3_default = {
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0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
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0x0079, 0x0888A39B, 0x26517FDA, 0x501F84EF, 0x00100206, 0x61A44A32,
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0x0000093B, 0x0000014A,
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"default name @303MHz \0",
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"default marking \0",
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};
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#else
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/* etamin board */
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const struct ddr3_data ddr3_default = {
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0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F,
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0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2,
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0x0000093B, 0x0000018A,
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"test-etamin \0",
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"generic-8Gbit \0",
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};
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#endif
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#elif DDR_PLL_FREQ == 400
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/* Default@400MHz-i0 */
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const struct ddr3_data ddr3_default = {
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0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
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0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
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0x00000618, 0x0000014A,
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"default name @400MHz \0",
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"default marking \0",
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};
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#endif
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static void set_default_ddr3_timings(void)
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{
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printf("Set default DDR3 settings\n");
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settings.ddr3 = ddr3_default;
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}
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static void print_ddr3_timings(void)
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{
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printf("\nDDR3\n");
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printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
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printf("device:\t\t%s\n", settings.ddr3.manu_name);
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printf("marking:\t%s\n", settings.ddr3.manu_marking);
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printf("%-20s, %-8s, %-8s, %-4s\n", "timing parameters", "eeprom",
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"default", "diff");
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PRINTARGS(magic);
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PRINTARGS(version);
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PRINTARGS(ddr3_sratio);
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PRINTARGS(iclkout);
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PRINTARGS(dt0rdsratio0);
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PRINTARGS(dt0wdsratio0);
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PRINTARGS(dt0fwsratio0);
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PRINTARGS(dt0wrsratio0);
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PRINTARGS(sdram_tim1);
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PRINTARGS(sdram_tim2);
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PRINTARGS(sdram_tim3);
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PRINTARGS(emif_ddr_phy_ctlr_1);
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PRINTARGS(sdram_config);
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PRINTARGS(ref_ctrl);
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PRINTARGS(ioctr_val);
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}
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static void print_chip_data(void)
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{
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struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
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printf("\nCPU BOARD\n");
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printf("device: \t'%s'\n", settings.chip.sdevname);
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printf("hw version: \t'%s'\n", settings.chip.shwver);
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printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m);
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}
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#endif /* CONFIG_SPL_BUILD */
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#define AM335X_NAND_ECC_MASK 0x0f
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#define AM335X_NAND_ECC_TYPE_16 0x02
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static int ecc_type;
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struct am335x_nand_geometry {
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u32 magic;
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u8 nand_geo_addr;
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u8 nand_geo_page;
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u8 nand_bus;
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};
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static int draco_read_nand_geometry(void)
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{
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struct am335x_nand_geometry geo;
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/* Read NAND geometry */
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2,
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(uchar *)&geo, sizeof(struct am335x_nand_geometry))) {
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printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n");
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return -EIO;
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}
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if (geo.magic != 0xa657b310) {
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printf("%s: bad magic: %x\n", __func__, geo.magic);
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return -EFAULT;
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}
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if ((geo.nand_bus & AM335X_NAND_ECC_MASK) == AM335X_NAND_ECC_TYPE_16)
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ecc_type = 16;
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else
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ecc_type = 8;
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return 0;
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}
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/*
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* Read header information from EEPROM into global structure.
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*/
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static int read_eeprom(void)
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{
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/* Check if baseboard eeprom is available */
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if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
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printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
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return 1;
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}
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#ifdef CONFIG_SPL_BUILD
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/* Read Siemens eeprom data (DDR3) */
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
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(uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
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printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
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set_default_ddr3_timings();
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}
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/* Read Siemens eeprom data (CHIP) */
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
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(uchar *)&settings.chip, sizeof(settings.chip)))
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printf("Could not read chip settings\n");
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if (ddr3_default.magic == settings.ddr3.magic &&
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ddr3_default.version == settings.ddr3.version) {
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printf("Using DDR3 settings from EEPROM\n");
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} else {
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if (ddr3_default.magic != settings.ddr3.magic)
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printf("Warning: No valid DDR3 data in eeprom.\n");
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if (ddr3_default.version != settings.ddr3.version)
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printf("Warning: DDR3 data version does not match.\n");
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printf("Using default settings\n");
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set_default_ddr3_timings();
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}
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if (MAGIC_CHIP == settings.chip.magic)
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print_chip_data();
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else
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printf("Warning: No chip data in eeprom\n");
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print_ddr3_timings();
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return draco_read_nand_geometry();
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#endif
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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static void board_init_ddr(void)
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{
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struct emif_regs draco_ddr3_emif_reg_data = {
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.zq_config = 0x50074BE4,
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};
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struct ddr_data draco_ddr3_data = {
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};
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struct cmd_control draco_ddr3_cmd_ctrl_data = {
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};
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struct ctrl_ioregs draco_ddr3_ioregs = {
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};
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/* pass values from eeprom */
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draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
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draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
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draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
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draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
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settings.ddr3.emif_ddr_phy_ctlr_1;
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draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
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draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000;
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draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
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draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
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draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
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draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
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draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
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draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
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draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
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draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
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draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
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draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
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draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
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draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
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draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
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draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
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draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
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draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
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config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
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&draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
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}
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static void spl_siemens_board_init(void)
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{
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return;
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}
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#endif /* if def CONFIG_SPL_BUILD */
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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int ret;
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ret = draco_read_nand_geometry();
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if (ret != 0)
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return ret;
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nand_curr_device = 0;
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omap_nand_switch_ecc(1, ecc_type);
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#ifdef CONFIG_TARGET_ETAMIN
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nand_curr_device = 1;
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omap_nand_switch_ecc(1, ecc_type);
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#endif
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#ifdef CONFIG_FACTORYSET
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/* Set ASN in environment*/
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if (factory_dat.asn[0] != 0) {
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env_set("dtb_name", (char *)factory_dat.asn);
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} else {
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/* dtb suffix gets added in load script */
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env_set("dtb_name", "am335x-draco");
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}
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#else
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env_set("dtb_name", "am335x-draco");
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#endif
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return 0;
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}
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#endif
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#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
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static void cpsw_control(int enabled)
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{
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/* VTP can be added here */
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return;
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}
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_addr = 0,
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.phy_if = PHY_INTERFACE_MODE_MII,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = CPSW_MDIO_BASE,
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.cpsw_base = CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 4,
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.cpdma_reg_ofs = 0x800,
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.slaves = 1,
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.slave_data = cpsw_slaves,
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.ale_reg_ofs = 0xd00,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x108,
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.hw_stats_reg_ofs = 0x900,
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.bd_ram_ofs = 0x2000,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_2,
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};
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#if defined(CONFIG_DRIVER_TI_CPSW) || \
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(defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
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int board_eth_init(bd_t *bis)
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{
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struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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int n = 0;
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int rv;
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factoryset_env_set();
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/* Set rgmii mode and enable rmii clock to be sourced from chip */
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writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
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rv = cpsw_register(&cpsw_data);
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if (rv < 0)
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printf("Error %d registering CPSW switch\n", rv);
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else
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n += rv;
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return n;
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}
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static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
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char *const argv[])
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{
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/* Reset SMSC LAN9303 switch for default configuration */
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gpio_request(GPIO_LAN9303_NRST, "nRST");
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gpio_direction_output(GPIO_LAN9303_NRST, 0);
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/* assert active low reset for 200us */
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udelay(200);
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gpio_set_value(GPIO_LAN9303_NRST, 1);
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return 0;
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};
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U_BOOT_CMD(
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switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset,
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"Reset LAN9303 switch via its reset pin",
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""
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);
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#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
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#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
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#ifdef CONFIG_NAND_CS_INIT
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/* GPMC definitions for second nand cs1 */
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static const u32 gpmc_nand_config[] = {
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ETAMIN_NAND_GPMC_CONFIG1,
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ETAMIN_NAND_GPMC_CONFIG2,
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ETAMIN_NAND_GPMC_CONFIG3,
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ETAMIN_NAND_GPMC_CONFIG4,
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ETAMIN_NAND_GPMC_CONFIG5,
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ETAMIN_NAND_GPMC_CONFIG6,
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/*CONFIG7- computed as params */
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};
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static void board_nand_cs_init(void)
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{
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enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1],
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0x18000000, GPMC_SIZE_16M);
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}
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#endif
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#include "../common/board.c"
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