mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-01 15:53:46 +09:00
2be296538e
This converts the following to Kconfig: CONFIG_ENV_IS_IN_MMC CONFIG_ENV_IS_IN_NAND CONFIG_ENV_IS_IN_UBI CONFIG_ENV_IS_NOWHERE In fact this already exists for sunxi as a 'choice' config. However not all the choices are available in Kconfig yet so we cannot use that. It would lead to more than one option being set. In addition, one purpose of this series is to allow the environment to be stored in more than one place. So the existing choice is converted to a normal config allowing each option to be set independently. There are not many opportunities for Kconfig updates to reduce the size of this patch. This was tested with ./tools/moveconfig.py -i CONFIG_ENV_IS_IN_MMC And then manual updates. This is because for CHAIN_OF_TRUST boards they can only have ENV_IS_NOWHERE set, so we enforce that via Kconfig logic now. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
135 lines
3.4 KiB
C
135 lines
3.4 KiB
C
/*
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* Configuration settings for the SAMA5D2 PTC Engineering board.
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*
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* Copyright (C) 2016 Atmel
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* Wenyou Yang <wenyou.yang@atmel.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include "at91-sama5_common.h"
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/* serial console */
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#define CONFIG_ATMEL_USART
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#define CONFIG_USART_BASE ATMEL_BASE_UART0
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#define CONFIG_USART_ID ATMEL_ID_UART0
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
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#define CONFIG_SYS_SDRAM_SIZE 0x20000000
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_INIT_SP_ADDR 0x210000
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#else
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
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#endif
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#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
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#undef CONFIG_AT91_GPIO
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#define CONFIG_ATMEL_PIO4
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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/* SerialFlash */
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#ifdef CONFIG_CMD_SF
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#define CONFIG_ATMEL_SPI
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#define CONFIG_SPI_FLASH_ATMEL
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#define CONFIG_SF_DEFAULT_BUS 0
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#define CONFIG_SF_DEFAULT_CS 0
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#define CONFIG_SF_DEFAULT_SPEED 30000000
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#endif
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/* NAND flash */
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#define CONFIG_CMD_NAND
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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/* PMECC & PMERRLOC */
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#define CONFIG_ATMEL_NAND_HWECC
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#define CONFIG_ATMEL_NAND_HW_PMECC
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#define CONFIG_CMD_NAND_TRIMFFS
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#endif
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/* USB */
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#define CONFIG_CMD_USB
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#ifdef CONFIG_CMD_USB
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#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
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#endif
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/* USB device */
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#define CONFIG_USB_GADGET
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#define CONFIG_USB_GADGET_DUALSPEED
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#define CONFIG_USB_GADGET_ATMEL_USBA
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#define CONFIG_USB_ETHER
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#define CONFIG_USB_ETH_RNDIS
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#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D2_PTC"
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/* Ethernet Hardware */
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#define CONFIG_MACB
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#define CONFIG_RMII
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_MACB_SEARCH_PHY
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#ifdef CONFIG_SYS_USE_NANDFLASH
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#undef CONFIG_ENV_OFFSET
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#undef CONFIG_ENV_OFFSET_REDUND
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#undef CONFIG_BOOTCOMMAND
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/* u-boot env in nand flash */
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#define CONFIG_ENV_OFFSET 0x200000
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#define CONFIG_ENV_OFFSET_REDUND 0x400000
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#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0xb80000 0x80000;" \
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"nand read 0x22000000 0x600000 0x600000;" \
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"bootz 0x22000000 - 0x21000000"
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#endif
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTARGS \
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"console=ttyS0,57600 earlyprintk " \
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"mtdparts=atmel_nand:6M(bootstrap)ro, 6M(kernel)ro,-(rootfs) " \
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"rootfstype=ubifs ubi.mtd=2 root=ubi0:rootfs"
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/* SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TEXT_BASE 0x200000
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#define CONFIG_SPL_MAX_SIZE 0x10000
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#define CONFIG_SPL_BSS_START_ADDR 0x20000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
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#define CONFIG_SYS_MONITOR_LEN (512 << 10)
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#ifdef CONFIG_SYS_USE_SERIALFLASH
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
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#elif CONFIG_SYS_USE_NANDFLASH
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_PMECC_CAP 8
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#define CONFIG_PMECC_SECTOR_SIZE 512
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_OOBSIZE 224
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#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
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#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
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#endif
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#endif
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