mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 22:26:16 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
91 lines
2.8 KiB
C
91 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Those values and defines are taken from the Marvell U-Boot version
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* "u-boot-2013.01-2014_T2.0" for the board Armada 375 DB-88F6720
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*/
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#define DB_88F6720_MPP0_7 0x00020020 /* SPI */
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#define DB_88F6720_MPP8_15 0x22000022 /* SPI , I2C */
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#define DB_88F6720_MPP16_23 0x22222222 /* UART, TDM*/
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#define DB_88F6720_MPP24_31 0x33333333 /* SDIO, SPI1*/
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#define DB_88F6720_MPP32_39 0x04403330 /* SPI1, External SMI */
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#define DB_88F6720_MPP40_47 0x22002044 /* UART1, GE0, SATA0 LED */
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#define DB_88F6720_MPP48_55 0x22222222 /* GE0 */
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#define DB_88F6720_MPP56_63 0x04444422 /* GE0 , LED_MATRIX, GPIO */
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#define DB_88F6720_MPP64_67 0x014 /* LED_MATRIX, SATA1 LED*/
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#define DB_88F6720_GPP_OUT_ENA_LOW 0xFFFFFFFF
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#define DB_88F6720_GPP_OUT_ENA_MID 0x7FFFFFFF
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#define DB_88F6720_GPP_OUT_ENA_HIGH 0xFFFFFFFF
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#define DB_88F6720_GPP_OUT_VAL_LOW 0x0
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#define DB_88F6720_GPP_OUT_VAL_MID BIT(31) /* SATA Power output enable */
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#define DB_88F6720_GPP_OUT_VAL_HIGH 0x0
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#define DB_88F6720_GPP_POL_LOW 0x0
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#define DB_88F6720_GPP_POL_MID 0x0
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#define DB_88F6720_GPP_POL_HIGH 0x0
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int board_early_init_f(void)
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{
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/* Configure MPP */
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writel(DB_88F6720_MPP0_7, MVEBU_MPP_BASE + 0x00);
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writel(DB_88F6720_MPP8_15, MVEBU_MPP_BASE + 0x04);
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writel(DB_88F6720_MPP16_23, MVEBU_MPP_BASE + 0x08);
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writel(DB_88F6720_MPP24_31, MVEBU_MPP_BASE + 0x0c);
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writel(DB_88F6720_MPP32_39, MVEBU_MPP_BASE + 0x10);
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writel(DB_88F6720_MPP40_47, MVEBU_MPP_BASE + 0x14);
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writel(DB_88F6720_MPP48_55, MVEBU_MPP_BASE + 0x18);
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writel(DB_88F6720_MPP56_63, MVEBU_MPP_BASE + 0x1c);
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writel(DB_88F6720_MPP64_67, MVEBU_MPP_BASE + 0x20);
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/* Configure GPIO */
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/* Set GPP Out value */
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writel(DB_88F6720_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
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writel(DB_88F6720_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
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writel(DB_88F6720_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
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/* Set GPP Polarity */
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writel(DB_88F6720_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
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writel(DB_88F6720_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
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writel(DB_88F6720_GPP_POL_HIGH, MVEBU_GPIO2_BASE + 0x0c);
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/* Set GPP Out Enable */
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writel(DB_88F6720_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
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writel(DB_88F6720_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
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writel(DB_88F6720_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: Marvell DB-88F6720\n");
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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cpu_eth_init(bis); /* Built in controller(s) come first */
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return pci_eth_init(bis);
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}
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