mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
953ab736af
Previous uDoo configuration adopts register settings for DDR3, clock, muxing, etc. taken from Nitrogen6x. uDoo schematics is rather different from that board, and it needs customized setting for most of the registers. All this changes can be considered atomical since it is part of initial support of the board. Patch changes uDoo configuration files path to a specific one, and adopt optimized value for every configured register. Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
56 lines
1.6 KiB
INI
56 lines
1.6 KiB
INI
/*
|
|
* Copyright (C) 2013 Boundary Devices
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
|
|
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
|
|
|
|
DATA 4, MX6_MMDC_P0_MDCFG0, 0x54597955
|
|
DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
|
|
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
|
|
|
|
DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
|
|
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
|
|
|
|
DATA 4, MX6_MMDC_P0_MDOR, 0x00591023
|
|
DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
|
|
DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
|
|
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
|
|
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
|
|
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003
|
|
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003
|
|
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
|
|
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
|
|
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
|
|
|
|
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43510360
|
|
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0342033F
|
|
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x033F033F
|
|
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03290266
|
|
|
|
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B3E4141
|
|
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x47413B4A
|
|
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x42404843
|
|
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4C3F4C45
|
|
|
|
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00350035
|
|
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
|
|
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00010001
|
|
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00010001
|
|
|
|
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
|
|
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
|
|
|
|
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
|
|
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
|
|
|