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https://github.com/brain-hackers/u-boot-brain
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41410eee47
Change UEC phy interface from GMII to RGMII on MPC8568MDS board Because on MPC8568MDS, GMII interface is only recommended for 1000Mbps speed, but RGMII interface can work at 10/100/1000Mbps, and RGMII interface works more stable. Now both UEC1 and UEC2 can work properly under u-boot. It is also in consistent with the kernel setting for 8568 UEC phy interface. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
273 lines
8.7 KiB
C
273 lines
8.7 KiB
C
/*
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* Copyright (C) 2005 Freescale Semiconductor, Inc.
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*
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* Author: Shlomi Gridish <gridish@freescale.com>
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*
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* Description: UCC ethernet driver -- PHY handling
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* Driver for UEC on QE
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* Based on 8260_io/fcc_enet.c
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef __UEC_PHY_H__
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#define __UEC_PHY_H__
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#define MII_end ((u32)-2)
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#define MII_read ((u32)-1)
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#define MIIMIND_BUSY 0x00000001
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#define MIIMIND_NOTVALID 0x00000004
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#define UGETH_AN_TIMEOUT 2000
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/* 1000BT control (Marvell & BCM54xx at least) */
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#define MII_1000BASETCONTROL 0x09
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#define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200
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#define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100
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/* 1000BT status */
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#define MII_1000BASETSTATUS 0x0a
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#define LPA_1000FULL 0x0400
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#define LPA_1000HALF 0x0200
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/* Cicada Extended Control Register 1 */
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#define MII_CIS8201_EXT_CON1 0x17
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#define MII_CIS8201_EXTCON1_INIT 0x0000
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/* Cicada Interrupt Mask Register */
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#define MII_CIS8201_IMASK 0x19
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#define MII_CIS8201_IMASK_IEN 0x8000
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#define MII_CIS8201_IMASK_SPEED 0x4000
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#define MII_CIS8201_IMASK_LINK 0x2000
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#define MII_CIS8201_IMASK_DUPLEX 0x1000
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#define MII_CIS8201_IMASK_MASK 0xf000
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/* Cicada Interrupt Status Register */
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#define MII_CIS8201_ISTAT 0x1a
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#define MII_CIS8201_ISTAT_STATUS 0x8000
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#define MII_CIS8201_ISTAT_SPEED 0x4000
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#define MII_CIS8201_ISTAT_LINK 0x2000
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#define MII_CIS8201_ISTAT_DUPLEX 0x1000
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/* Cicada Auxiliary Control/Status Register */
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#define MII_CIS8201_AUX_CONSTAT 0x1c
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#define MII_CIS8201_AUXCONSTAT_INIT 0x0004
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#define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020
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#define MII_CIS8201_AUXCONSTAT_SPEED 0x0018
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#define MII_CIS8201_AUXCONSTAT_GBIT 0x0010
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#define MII_CIS8201_AUXCONSTAT_100 0x0008
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/* 88E1011 PHY Status Register */
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#define MII_M1011_PHY_SPEC_STATUS 0x11
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#define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
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#define MII_M1011_PHY_SPEC_STATUS_100 0x4000
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#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
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#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
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#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
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#define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400
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#define MII_M1011_IEVENT 0x13
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#define MII_M1011_IEVENT_CLEAR 0x0000
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#define MII_M1011_IMASK 0x12
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#define MII_M1011_IMASK_INIT 0x6400
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#define MII_M1011_IMASK_CLEAR 0x0000
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/* 88E1111 PHY Register */
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#define MII_M1111_PHY_EXT_CR 0x14
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#define MII_M1111_RX_DELAY 0x80
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#define MII_M1111_TX_DELAY 0x2
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#define MII_M1111_PHY_EXT_SR 0x1b
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#define MII_M1111_HWCFG_MODE_MASK 0xf
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#define MII_M1111_HWCFG_MODE_RGMII 0xb
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#define MII_DM9161_SCR 0x10
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#define MII_DM9161_SCR_INIT 0x0610
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#define MII_DM9161_SCR_RMII_INIT 0x0710
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/* DM9161 Specified Configuration and Status Register */
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#define MII_DM9161_SCSR 0x11
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#define MII_DM9161_SCSR_100F 0x8000
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#define MII_DM9161_SCSR_100H 0x4000
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#define MII_DM9161_SCSR_10F 0x2000
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#define MII_DM9161_SCSR_10H 0x1000
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/* DM9161 Interrupt Register */
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#define MII_DM9161_INTR 0x15
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#define MII_DM9161_INTR_PEND 0x8000
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#define MII_DM9161_INTR_DPLX_MASK 0x0800
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#define MII_DM9161_INTR_SPD_MASK 0x0400
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#define MII_DM9161_INTR_LINK_MASK 0x0200
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#define MII_DM9161_INTR_MASK 0x0100
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#define MII_DM9161_INTR_DPLX_CHANGE 0x0010
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#define MII_DM9161_INTR_SPD_CHANGE 0x0008
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#define MII_DM9161_INTR_LINK_CHANGE 0x0004
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#define MII_DM9161_INTR_INIT 0x0000
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#define MII_DM9161_INTR_STOP \
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(MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \
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| MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
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/* DM9161 10BT Configuration/Status */
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#define MII_DM9161_10BTCSR 0x12
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#define MII_DM9161_10BTCSR_INIT 0x7800
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#define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
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SUPPORTED_10baseT_Full | \
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SUPPORTED_100baseT_Half | \
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SUPPORTED_100baseT_Full | \
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SUPPORTED_Autoneg | \
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SUPPORTED_TP | \
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SUPPORTED_MII)
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#define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \
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SUPPORTED_1000baseT_Half | \
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SUPPORTED_1000baseT_Full)
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#define MII_READ_COMMAND 0x00000001
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#define MII_INTERRUPT_DISABLED 0x0
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#define MII_INTERRUPT_ENABLED 0x1
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#define SPEED_10 10
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#define SPEED_100 100
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#define SPEED_1000 1000
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/* Duplex, half or full. */
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#define DUPLEX_HALF 0x00
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#define DUPLEX_FULL 0x01
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/* Indicates what features are supported by the interface. */
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#define SUPPORTED_10baseT_Half (1 << 0)
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#define SUPPORTED_10baseT_Full (1 << 1)
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#define SUPPORTED_100baseT_Half (1 << 2)
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#define SUPPORTED_100baseT_Full (1 << 3)
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#define SUPPORTED_1000baseT_Half (1 << 4)
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#define SUPPORTED_1000baseT_Full (1 << 5)
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#define SUPPORTED_Autoneg (1 << 6)
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#define SUPPORTED_TP (1 << 7)
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#define SUPPORTED_AUI (1 << 8)
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#define SUPPORTED_MII (1 << 9)
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#define SUPPORTED_FIBRE (1 << 10)
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#define SUPPORTED_BNC (1 << 11)
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#define SUPPORTED_10000baseT_Full (1 << 12)
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#define ADVERTISED_10baseT_Half (1 << 0)
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#define ADVERTISED_10baseT_Full (1 << 1)
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#define ADVERTISED_100baseT_Half (1 << 2)
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#define ADVERTISED_100baseT_Full (1 << 3)
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#define ADVERTISED_1000baseT_Half (1 << 4)
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#define ADVERTISED_1000baseT_Full (1 << 5)
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#define ADVERTISED_Autoneg (1 << 6)
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#define ADVERTISED_TP (1 << 7)
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#define ADVERTISED_AUI (1 << 8)
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#define ADVERTISED_MII (1 << 9)
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#define ADVERTISED_FIBRE (1 << 10)
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#define ADVERTISED_BNC (1 << 11)
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#define ADVERTISED_10000baseT_Full (1 << 12)
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/* Advertisement control register. */
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#define ADVERTISE_SLCT 0x001f /* Selector bits */
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#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
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#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
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#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
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#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
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#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
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#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
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#define ADVERTISE_RESV 0x1c00 /* Unused... */
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#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
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#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
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#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
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#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
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ADVERTISE_CSMA)
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#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
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ADVERTISE_100HALF | ADVERTISE_100FULL)
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/* Taken from mii_if_info and sungem_phy.h */
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struct uec_mii_info {
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/* Information about the PHY type */
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/* And management functions */
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struct phy_info *phyinfo;
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struct eth_device *dev;
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/* forced speed & duplex (no autoneg)
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* partner speed & duplex & pause (autoneg)
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*/
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int speed;
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int duplex;
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int pause;
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/* The most recently read link state */
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int link;
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/* Enabled Interrupts */
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u32 interrupts;
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u32 advertising;
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int autoneg;
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int mii_id;
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/* private data pointer */
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/* For use by PHYs to maintain extra state */
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void *priv;
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/* Provided by ethernet driver */
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int (*mdio_read) (struct eth_device * dev, int mii_id, int reg);
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void (*mdio_write) (struct eth_device * dev, int mii_id, int reg,
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int val);
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};
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/* struct phy_info: a structure which defines attributes for a PHY
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*
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* id will contain a number which represents the PHY. During
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* startup, the driver will poll the PHY to find out what its
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* UID--as defined by registers 2 and 3--is. The 32-bit result
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* gotten from the PHY will be ANDed with phy_id_mask to
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* discard any bits which may change based on revision numbers
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* unimportant to functionality
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*
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* There are 6 commands which take a ugeth_mii_info structure.
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* Each PHY must declare config_aneg, and read_status.
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*/
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struct phy_info {
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u32 phy_id;
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char *name;
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unsigned int phy_id_mask;
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u32 features;
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/* Called to initialize the PHY */
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int (*init) (struct uec_mii_info * mii_info);
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/* Called to suspend the PHY for power */
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int (*suspend) (struct uec_mii_info * mii_info);
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/* Reconfigures autonegotiation (or disables it) */
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int (*config_aneg) (struct uec_mii_info * mii_info);
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/* Determines the negotiated speed and duplex */
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int (*read_status) (struct uec_mii_info * mii_info);
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/* Clears any pending interrupts */
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int (*ack_interrupt) (struct uec_mii_info * mii_info);
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/* Enables or disables interrupts */
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int (*config_intr) (struct uec_mii_info * mii_info);
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/* Clears up any memory if needed */
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void (*close) (struct uec_mii_info * mii_info);
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};
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struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info);
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void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
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int value);
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int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
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void mii_clear_phy_interrupt (struct uec_mii_info *mii_info);
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void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
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u32 interrupts);
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#endif /* __UEC_PHY_H__ */
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