mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 10:46:15 +09:00
d93d0f0cfe
This patch is intended to prepare the other S5P SoC. (s5pc210) If use SoC specific defines then can't share with other SoC. So, make the accessor functions for access the base address by common way. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
469 lines
10 KiB
C
469 lines
10 KiB
C
/*
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* (C) Copyright 2009 SAMSUNG Electronics
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* Minkyu Kang <mk7.kang@samsung.com>
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* Jaehoon Chung <jh80.chung@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mmc.h>
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#include <asm/io.h>
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#include <asm/arch/mmc.h>
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/* support 4 mmc hosts */
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struct mmc mmc_dev[4];
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struct mmc_host mmc_host[4];
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static inline struct s5p_mmc *s5p_get_base_mmc(int dev_index)
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{
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unsigned long offset = dev_index * sizeof(struct s5p_mmc);
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return (struct s5p_mmc *)(samsung_get_base_mmc() + offset);
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}
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static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
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{
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unsigned char ctrl;
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debug("data->dest: %08x\n", (u32)data->dest);
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writel((u32)data->dest, &host->reg->sysad);
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/*
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* DMASEL[4:3]
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* 00 = Selects SDMA
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* 01 = Reserved
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* 10 = Selects 32-bit Address ADMA2
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* 11 = Selects 64-bit Address ADMA2
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*/
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ctrl = readb(&host->reg->hostctl);
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ctrl &= ~(3 << 3);
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writeb(ctrl, &host->reg->hostctl);
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/* We do not handle DMA boundaries, so set it to max (512 KiB) */
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writew((7 << 12) | (512 << 0), &host->reg->blksize);
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writew(data->blocks, &host->reg->blkcnt);
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}
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static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
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{
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unsigned short mode;
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/*
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* TRNMOD
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* MUL1SIN0[5] : Multi/Single Block Select
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* RD1WT0[4] : Data Transfer Direction Select
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* 1 = read
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* 0 = write
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* ENACMD12[2] : Auto CMD12 Enable
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* ENBLKCNT[1] : Block Count Enable
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* ENDMA[0] : DMA Enable
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*/
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mode = (1 << 1) | (1 << 0);
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if (data->blocks > 1)
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mode |= (1 << 5);
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if (data->flags & MMC_DATA_READ)
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mode |= (1 << 4);
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writew(mode, &host->reg->trnmod);
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}
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static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct mmc_host *host = (struct mmc_host *)mmc->priv;
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int flags, i;
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unsigned int timeout;
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unsigned int mask;
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unsigned int retry = 0x100000;
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/* Wait max 10 ms */
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timeout = 10;
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/*
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* PRNSTS
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* CMDINHDAT[1] : Command Inhibit (DAT)
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* CMDINHCMD[0] : Command Inhibit (CMD)
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*/
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mask = (1 << 0);
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if ((data != NULL) || (cmd->resp_type & MMC_RSP_BUSY))
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mask |= (1 << 1);
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/*
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* We shouldn't wait for data inihibit for stop commands, even
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* though they might use busy signaling
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*/
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if (data)
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mask &= ~(1 << 1);
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while (readl(&host->reg->prnsts) & mask) {
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if (timeout == 0) {
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printf("%s: timeout error\n", __func__);
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return -1;
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}
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timeout--;
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udelay(1000);
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}
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if (data)
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mmc_prepare_data(host, data);
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debug("cmd->arg: %08x\n", cmd->cmdarg);
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writel(cmd->cmdarg, &host->reg->argument);
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if (data)
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mmc_set_transfer_mode(host, data);
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if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
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return -1;
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/*
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* CMDREG
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* CMDIDX[13:8] : Command index
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* DATAPRNT[5] : Data Present Select
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* ENCMDIDX[4] : Command Index Check Enable
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* ENCMDCRC[3] : Command CRC Check Enable
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* RSPTYP[1:0]
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* 00 = No Response
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* 01 = Length 136
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* 10 = Length 48
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* 11 = Length 48 Check busy after response
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*/
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if (!(cmd->resp_type & MMC_RSP_PRESENT))
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flags = 0;
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else if (cmd->resp_type & MMC_RSP_136)
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flags = (1 << 0);
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else if (cmd->resp_type & MMC_RSP_BUSY)
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flags = (3 << 0);
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else
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flags = (2 << 0);
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if (cmd->resp_type & MMC_RSP_CRC)
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flags |= (1 << 3);
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if (cmd->resp_type & MMC_RSP_OPCODE)
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flags |= (1 << 4);
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if (data)
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flags |= (1 << 5);
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debug("cmd: %d\n", cmd->cmdidx);
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writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
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for (i = 0; i < retry; i++) {
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mask = readl(&host->reg->norintsts);
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/* Command Complete */
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if (mask & (1 << 0)) {
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if (!data)
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writel(mask, &host->reg->norintsts);
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break;
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}
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}
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if (i == retry) {
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printf("%s: waiting for status update\n", __func__);
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return TIMEOUT;
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}
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if (mask & (1 << 16)) {
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/* Timeout Error */
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debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
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return TIMEOUT;
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} else if (mask & (1 << 15)) {
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/* Error Interrupt */
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debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
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return -1;
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}
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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if (cmd->resp_type & MMC_RSP_136) {
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/* CRC is stripped so we need to do some shifting. */
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for (i = 0; i < 4; i++) {
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unsigned int offset =
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(unsigned int)(&host->reg->rspreg3 - i);
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cmd->response[i] = readl(offset) << 8;
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if (i != 3) {
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cmd->response[i] |=
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readb(offset - 1);
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}
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debug("cmd->resp[%d]: %08x\n",
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i, cmd->response[i]);
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}
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} else if (cmd->resp_type & MMC_RSP_BUSY) {
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for (i = 0; i < retry; i++) {
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/* PRNTDATA[23:20] : DAT[3:0] Line Signal */
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if (readl(&host->reg->prnsts)
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& (1 << 20)) /* DAT[0] */
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break;
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}
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if (i == retry) {
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printf("%s: card is still busy\n", __func__);
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return TIMEOUT;
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}
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cmd->response[0] = readl(&host->reg->rspreg0);
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debug("cmd->resp[0]: %08x\n", cmd->response[0]);
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} else {
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cmd->response[0] = readl(&host->reg->rspreg0);
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debug("cmd->resp[0]: %08x\n", cmd->response[0]);
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}
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}
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if (data) {
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while (1) {
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mask = readl(&host->reg->norintsts);
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if (mask & (1 << 15)) {
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/* Error Interrupt */
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writel(mask, &host->reg->norintsts);
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printf("%s: error during transfer: 0x%08x\n",
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__func__, mask);
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return -1;
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} else if (mask & (1 << 3)) {
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/* DMA Interrupt */
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debug("DMA end\n");
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break;
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} else if (mask & (1 << 1)) {
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/* Transfer Complete */
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debug("r/w is done\n");
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break;
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}
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}
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writel(mask, &host->reg->norintsts);
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}
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udelay(1000);
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return 0;
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}
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static void mmc_change_clock(struct mmc_host *host, uint clock)
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{
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int div;
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unsigned short clk;
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unsigned long timeout;
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unsigned long ctrl2;
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/*
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* SELBASECLK[5:4]
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* 00/01 = HCLK
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* 10 = EPLL
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* 11 = XTI or XEXTCLK
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*/
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ctrl2 = readl(&host->reg->control2);
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ctrl2 &= ~(3 << 4);
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ctrl2 |= (2 << 4);
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writel(ctrl2, &host->reg->control2);
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writew(0, &host->reg->clkcon);
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/* XXX: we assume that clock is between 40MHz and 50MHz */
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if (clock == 0)
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goto out;
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else if (clock <= 400000)
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div = 0x100;
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else if (clock <= 20000000)
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div = 4;
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else if (clock <= 26000000)
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div = 2;
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else
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div = 1;
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debug("div: %d\n", div);
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div >>= 1;
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/*
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* CLKCON
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* SELFREQ[15:8] : base clock divied by value
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* ENSDCLK[2] : SD Clock Enable
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* STBLINTCLK[1] : Internal Clock Stable
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* ENINTCLK[0] : Internal Clock Enable
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*/
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clk = (div << 8) | (1 << 0);
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writew(clk, &host->reg->clkcon);
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/* Wait max 10 ms */
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timeout = 10;
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while (!(readw(&host->reg->clkcon) & (1 << 1))) {
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if (timeout == 0) {
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printf("%s: timeout error\n", __func__);
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return;
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}
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timeout--;
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udelay(1000);
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}
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clk |= (1 << 2);
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writew(clk, &host->reg->clkcon);
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out:
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host->clock = clock;
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}
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static void mmc_set_ios(struct mmc *mmc)
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{
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struct mmc_host *host = mmc->priv;
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unsigned char ctrl;
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unsigned long val;
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debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
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/*
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* SELCLKPADDS[17:16]
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* 00 = 2mA
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* 01 = 4mA
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* 10 = 7mA
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* 11 = 9mA
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*/
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writel(0x3 << 16, &host->reg->control4);
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val = readl(&host->reg->control2);
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val &= (0x3 << 4);
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val |= (1 << 31) | /* write status clear async mode enable */
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(1 << 30) | /* command conflict mask enable */
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(1 << 14) | /* Feedback Clock Enable for Rx Clock */
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(1 << 8); /* SDCLK hold enable */
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writel(val, &host->reg->control2);
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/*
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* FCSEL1[15] FCSEL0[7]
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* FCSel[1:0] : Rx Feedback Clock Delay Control
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* Inverter delay means10ns delay if SDCLK 50MHz setting
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* 01 = Delay1 (basic delay)
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* 11 = Delay2 (basic delay + 2ns)
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* 00 = Delay3 (inverter delay)
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* 10 = Delay4 (inverter delay + 2ns)
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*/
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writel(0x8080, &host->reg->control3);
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mmc_change_clock(host, mmc->clock);
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ctrl = readb(&host->reg->hostctl);
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/*
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* WIDE4[1]
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* 1 = 4-bit mode
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* 0 = 1-bit mode
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*/
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if (mmc->bus_width == 4)
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ctrl |= (1 << 1);
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else
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ctrl &= ~(1 << 1);
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/*
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* OUTEDGEINV[2]
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* 1 = Riging edge output
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* 0 = Falling edge output
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*/
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ctrl &= ~(1 << 2);
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writeb(ctrl, &host->reg->hostctl);
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}
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static void mmc_reset(struct mmc_host *host)
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{
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unsigned int timeout;
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/*
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* RSTALL[0] : Software reset for all
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* 1 = reset
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* 0 = work
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*/
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writeb((1 << 0), &host->reg->swrst);
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host->clock = 0;
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/* Wait max 100 ms */
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timeout = 100;
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/* hw clears the bit when it's done */
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while (readb(&host->reg->swrst) & (1 << 0)) {
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if (timeout == 0) {
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printf("%s: timeout error\n", __func__);
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return;
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}
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timeout--;
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udelay(1000);
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}
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}
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static int mmc_core_init(struct mmc *mmc)
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{
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struct mmc_host *host = (struct mmc_host *)mmc->priv;
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unsigned int mask;
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mmc_reset(host);
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host->version = readw(&host->reg->hcver);
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/* mask all */
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writel(0xffffffff, &host->reg->norintstsen);
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writel(0xffffffff, &host->reg->norintsigen);
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writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */
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/*
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* NORMAL Interrupt Status Enable Register init
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* [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
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* [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
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* [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
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* [0] ENSTACMDCMPLT : Command Complete Status Enable
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*/
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mask = readl(&host->reg->norintstsen);
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mask &= ~(0xffff);
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mask |= (1 << 5) | (1 << 4) | (1 << 1) | (1 << 0);
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writel(mask, &host->reg->norintstsen);
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/*
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* NORMAL Interrupt Signal Enable Register init
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* [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
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*/
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mask = readl(&host->reg->norintsigen);
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mask &= ~(0xffff);
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mask |= (1 << 1);
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writel(mask, &host->reg->norintsigen);
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return 0;
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}
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static int s5p_mmc_initialize(int dev_index)
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{
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struct mmc *mmc;
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mmc = &mmc_dev[dev_index];
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sprintf(mmc->name, "SAMSUNG SD/MMC");
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mmc->priv = &mmc_host[dev_index];
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mmc->send_cmd = mmc_send_cmd;
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mmc->set_ios = mmc_set_ios;
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mmc->init = mmc_core_init;
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mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
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mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
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mmc->f_min = 400000;
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mmc->f_max = 52000000;
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mmc_host[dev_index].clock = 0;
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mmc_host[dev_index].reg = s5p_get_base_mmc(dev_index);
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mmc_register(mmc);
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return 0;
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}
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int s5p_mmc_init(int dev_index)
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{
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return s5p_mmc_initialize(dev_index);
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}
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