mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 03:36:16 +09:00
92a190aaab
With this change driver will benefit from existing phylib and thus custom phy functionality implemented in the driver will go away: * Instantiation of the driver is now much shorter - 2 parameters instead of 4. * Simplified phy management/functoinality in driver is replaced with rich functionality of phylib. * Support of custom phy initialization is now done with existing "board_phy_config". Note that after this change some previously used config options (driver-specific PHY configuration) will be obsolete and they are simply substituted with similar options of phylib. For example: * CONFIG_DW_AUTONEG - no need in this one. Autonegotiation is enabled by default. * CONFIG_DW_SEARCH_PHY - if one wants to specify attached phy explicitly CONFIG_PHY_ADDR board config option has to be used, otherwise automatically the first discovered on MDIO bus phy will be used I believe there's no need now in "doc/README.designware_eth" because user only needs to instantiate the driver with "designware_initialize" whose prototype exists in "include/netdev.h". Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Stefan Roese <sr@denx.de> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Amit Virdi <amit.virdi@st.com> Cc: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
110 lines
2.4 KiB
C
110 lines
2.4 KiB
C
/*
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* (C) Copyright 2009
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* Copyright (C) 2012 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <nand.h>
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#include <netdev.h>
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#include <phy.h>
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#include <rtc.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/spr_defs.h>
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#include <asm/arch/spr_misc.h>
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#include <linux/mtd/fsmc_nand.h>
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#include "fpga.h"
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static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
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int board_init(void)
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{
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/*
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* X600 is equipped with an M41T82 RTC. This RTC has the
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* HT bit (Halt Update), which needs to be cleared upon
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* power-up. Otherwise the RTC is halted.
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*/
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rtc_reset();
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return spear_board_init(MACH_TYPE_SPEAR600);
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}
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int board_late_init(void)
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{
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/*
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* Monitor and env protection on by default
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*/
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flash_protect(FLAG_PROTECT_SET,
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CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE +
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CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN +
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2 * CONFIG_ENV_SECT_SIZE - 1,
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&flash_info[0]);
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/* Init FPGA subsystem */
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x600_init_fpga();
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return 0;
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}
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/*
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* board_nand_init - Board specific NAND initialization
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* @nand: mtd private chip structure
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*
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* Called by nand_init_chip to initialize the board specific functions
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*/
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void board_nand_init(void)
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{
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struct misc_regs *const misc_regs_p =
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(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
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struct nand_chip *nand = &nand_chip[0];
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if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
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fsmc_nand_init(nand);
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}
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int board_phy_config(struct phy_device *phydev)
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{
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/* Extended PHY control 1, select GMII */
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phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
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/* Software reset necessary after GMII mode selction */
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phy_reset(phydev);
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/* Enable extended page register access */
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phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
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/* 17e: Enhanced LED behavior, needs to be written twice */
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phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
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phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
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/* 16e: Enhanced LED method select */
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phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
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/* Disable extended page register access */
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phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
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/* Enable clock output pin */
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phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int ret = 0;
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if (designware_initialize(CONFIG_SPEAR_ETHBASE,
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PHY_INTERFACE_MODE_GMII) >= 0)
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ret++;
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return ret;
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}
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