Thierry Reding aba11d4476 ARM: tegra124: Clear IDDQ when enabling PLLC ... Enabling a PLL while IDDQ is high. The Linux kernel checks for this condition and warns about it verbosely, so while this seems to work fine, fix it up according to the programming guidelines provided in the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup Sequence"). Reported-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>		2015-09-16 16:11:31 -07:00
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clock.c	ARM: tegra124: Clear IDDQ when enabling PLLC	2015-09-16 16:11:31 -07:00
cpu.c	Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.	2015-08-05 15:22:51 -07:00
funcmux.c	ARM: tegra: collect SoC sources into mach-tegra	2015-02-21 08:23:51 -05:00
Kconfig	tegra: Replace 'Norrin' with 'Nyan-big' and fix typo	2015-06-09 09:56:15 -07:00
Makefile	tegra124: Add PSCI support for Tegra124	2015-05-13 09:24:15 -07:00
pinmux.c	ARM: tegra: enable MIPI PAD CTRL support for Tegra124	2015-03-30 09:54:06 -07:00
psci.c	tegra124: Add PSCI support for Tegra124	2015-05-13 09:24:15 -07:00
xusb-padctl.c	ARM: tegra: collect SoC sources into mach-tegra	2015-02-21 08:23:51 -05:00