mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-31 23:33:44 +09:00
![]() SerDes PLL bandwidth default setting is incorrect when no lanes are configured as PCI Express. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
||
---|---|---|
.. | ||
asm |