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https://github.com/brain-hackers/u-boot-brain
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b9e745bbe2
This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future. Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/ LS1012AFRDM. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
160 lines
3.4 KiB
C
160 lines
3.4 KiB
C
/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef FSL_MMDC_H
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#define FSL_MMDC_H
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/* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */
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#define MPWLGCR_HW_WL_EN (1 << 0)
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/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
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#define MPPDCMPR2_MPR_COMPARE_EN (1 << 0)
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/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
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#define AUTO_RD_DQS_GATING_CALIBRATION_EN (1 << 28)
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/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
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#define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN (1 << 4)
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/* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */
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#define MMDC_MAPSR_PWR_SAV_CTRL_STAT 0x00001067
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/* MMDC Core Refresh Control Register (MMDC_MDREF) */
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#define MDREF_START_REFRESH (1 << 0)
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/* MMDC Core Special Command Register (MDSCR) */
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#define CMD_ADDR_MSB_MR_OP(x) (x << 24)
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#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
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#define MDSCR_DISABLE_CFG_REQ (0 << 15)
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#define MDSCR_ENABLE_CON_REQ (1 << 15)
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#define MDSCR_CON_ACK (1 << 14)
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#define MDSCR_WL_EN (1 << 9)
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#define CMD_NORMAL (0 << 4)
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#define CMD_PRECHARGE (1 << 4)
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#define CMD_AUTO_REFRESH (2 << 4)
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#define CMD_LOAD_MODE_REG (3 << 4)
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#define CMD_ZQ_CALIBRATION (4 << 4)
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#define CMD_PRECHARGE_BANK_OPEN (5 << 4)
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#define CMD_MRR (6 << 4)
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#define CMD_BANK_ADDR_0 0x0
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#define CMD_BANK_ADDR_1 0x1
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#define CMD_BANK_ADDR_2 0x2
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#define CMD_BANK_ADDR_3 0x3
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#define CMD_BANK_ADDR_4 0x4
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#define CMD_BANK_ADDR_5 0x5
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#define CMD_BANK_ADDR_6 0x6
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#define CMD_BANK_ADDR_7 0x7
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/* MMDC Core Control Register (MDCTL) */
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#define MDCTL_SDE0 (1 << 31)
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#define MDCTL_SDE1 (1 << 30)
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/* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */
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#define MPZQHWCTRL_ZQ_HW_FORCE (1 << 16)
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/* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */
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#define MMDC_MPMUR0_FRC_MSR (1 << 11)
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/* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */
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/* default 64 for a quarter cycle delay */
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#define MMDC_MPRDDLCTL_DEFAULT_DELAY 0x40404040
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/* MMDC Registers */
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struct mmdc_regs {
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u32 mdctl;
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u32 mdpdc;
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u32 mdotc;
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u32 mdcfg0;
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u32 mdcfg1;
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u32 mdcfg2;
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u32 mdmisc;
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u32 mdscr;
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u32 mdref;
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u32 res1[2];
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u32 mdrwd;
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u32 mdor;
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u32 mdmrr;
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u32 mdcfg3lp;
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u32 mdmr4;
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u32 mdasp;
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u32 res2[239];
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u32 maarcr;
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u32 mapsr;
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u32 maexidr0;
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u32 maexidr1;
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u32 madpcr0;
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u32 madpcr1;
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u32 madpsr0;
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u32 madpsr1;
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u32 madpsr2;
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u32 madpsr3;
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u32 madpsr4;
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u32 madpsr5;
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u32 masbs0;
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u32 masbs1;
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u32 res3[2];
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u32 magenp;
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u32 res4[239];
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u32 mpzqhwctrl;
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u32 mpzqswctrl;
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u32 mpwlgcr;
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u32 mpwldectrl0;
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u32 mpwldectrl1;
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u32 mpwldlst;
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u32 mpodtctrl;
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u32 mprddqby0dl;
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u32 mprddqby1dl;
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u32 mprddqby2dl;
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u32 mprddqby3dl;
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u32 mpwrdqby0dl;
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u32 mpwrdqby1dl;
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u32 mpwrdqby2dl;
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u32 mpwrdqby3dl;
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u32 mpdgctrl0;
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u32 mpdgctrl1;
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u32 mpdgdlst0;
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u32 mprddlctl;
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u32 mprddlst;
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u32 mpwrdlctl;
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u32 mpwrdlst;
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u32 mpsdctrl;
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u32 mpzqlp2ctl;
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u32 mprddlhwctl;
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u32 mpwrdlhwctl;
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u32 mprddlhwst0;
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u32 mprddlhwst1;
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u32 mpwrdlhwst0;
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u32 mpwrdlhwst1;
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u32 mpwlhwerr;
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u32 mpdghwst0;
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u32 mpdghwst1;
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u32 mpdghwst2;
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u32 mpdghwst3;
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u32 mppdcmpr1;
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u32 mppdcmpr2;
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u32 mpswdar0;
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u32 mpswdrdr0;
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u32 mpswdrdr1;
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u32 mpswdrdr2;
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u32 mpswdrdr3;
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u32 mpswdrdr4;
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u32 mpswdrdr5;
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u32 mpswdrdr6;
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u32 mpswdrdr7;
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u32 mpmur0;
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u32 mpwrcadl;
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u32 mpdccr;
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};
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void mmdc_init(void);
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#if !defined(CONFIG_MMDC_MDCTL)
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#error Must configure board-specific timing CONFIG_MMDC_* in <board>.h for MMDC
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#endif
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#endif /* FSL_MMDC_H */
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