mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 19:56:18 +09:00
436baaa2f5
This commit "2bb014820c49a63902103bac710bc86b5772e843" do some clean up to use the code in lib/time.c. But usec2ticks is still being used by security related job ring code. Bring back the function to avoid build break when CONFIG_FSL_CAAM is defined. The computation logic has been changed, using 64-bit variable to ease the process, making it work on older (MX5) platforms. Signed-off-by: Peng Fan <van.freenix@gmail.com> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
139 lines
3.0 KiB
C
139 lines
3.0 KiB
C
/*
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <div64.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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/* General purpose timers registers */
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struct mxc_gpt {
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unsigned int control;
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unsigned int prescaler;
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unsigned int status;
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unsigned int nouse[6];
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unsigned int counter;
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};
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static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
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/* General purpose timers bitfields */
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#define GPTCR_SWR (1 << 15) /* Software reset */
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#define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */
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#define GPTCR_FRR (1 << 9) /* Freerun / restart */
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#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */
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#define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */
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#define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */
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#define GPTCR_CLKSOURCE_MASK (0x7 << 6)
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#define GPTCR_TEN 1 /* Timer enable */
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#define GPTPR_PRESCALER24M_SHIFT 12
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#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
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DECLARE_GLOBAL_DATA_PTR;
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static inline int gpt_has_clk_source_osc(void)
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{
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#if defined(CONFIG_MX6)
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if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
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is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
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is_mx6ull())
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return 1;
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return 0;
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#else
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return 0;
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#endif
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}
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static inline ulong gpt_get_clk(void)
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{
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#ifdef CONFIG_MXC_GPT_HCLK
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if (gpt_has_clk_source_osc())
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return MXC_HCLK >> 3;
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else
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return mxc_get_clock(MXC_IPG_PERCLK);
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#else
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return MXC_CLK32;
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#endif
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}
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int timer_init(void)
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{
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int i;
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/* setup GP Timer 1 */
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__raw_writel(GPTCR_SWR, &cur_gpt->control);
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/* We have no udelay by now */
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for (i = 0; i < 100; i++)
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__raw_writel(0, &cur_gpt->control);
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i = __raw_readl(&cur_gpt->control);
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i &= ~GPTCR_CLKSOURCE_MASK;
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#ifdef CONFIG_MXC_GPT_HCLK
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if (gpt_has_clk_source_osc()) {
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i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
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/* For DL/S, SX, UL, ULL set 24Mhz OSC Enable bit and prescaler */
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if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull()) {
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i |= GPTCR_24MEN;
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/* Produce 3Mhz clock */
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__raw_writel((7 << GPTPR_PRESCALER24M_SHIFT),
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&cur_gpt->prescaler);
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}
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} else {
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i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN;
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}
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#else
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__raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
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i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
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#endif
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__raw_writel(i, &cur_gpt->control);
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gd->arch.tbl = __raw_readl(&cur_gpt->counter);
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gd->arch.tbu = 0;
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return 0;
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}
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unsigned long timer_read_counter(void)
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{
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return __raw_readl(&cur_gpt->counter); /* current tick value */
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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return gpt_get_clk();
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}
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/*
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* This function is intended for SHORT delays only.
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* It will overflow at around 10 seconds @ 400MHz,
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* or 20 seconds @ 200MHz.
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*/
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unsigned long usec2ticks(unsigned long _usec)
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{
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unsigned long long usec = _usec;
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usec *= get_tbclk();
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usec += 999999;
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do_div(usec, 1000000);
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return usec;
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}
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