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https://github.com/brain-hackers/u-boot-brain
synced 2024-09-03 11:23:22 +09:00
![Nick Spence](/assets/img/avatar_default.png)
Set DAT value before DIR values to avoid creating glitches on the GPIO signals. Set gpio level register before direction register to inhibit glitches on high level output pins. Dir and data gets cleared at powerup, so high level output lines see a short low pulse between setting the direction and level registers. Issue was seen on a new board with the nReset line of the NOR flash connected to a GPIO. Setting the direction register puts the NOR flash in reset so the next instruction to set the level cannot get executed. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
340 lines
9.2 KiB
C
340 lines
9.2 KiB
C
/*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc83xx.h>
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#include <ioports.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_QE
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extern qe_iop_conf_t qe_iop_conf_tab[];
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extern void qe_config_iopin(u8 port, u8 pin, int dir,
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int open_drain, int assign);
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extern void qe_init(uint qe_base);
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extern void qe_reset(void);
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static void config_qe_ioports(void)
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{
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u8 port, pin;
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int dir, open_drain, assign;
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int i;
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for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
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port = qe_iop_conf_tab[i].port;
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pin = qe_iop_conf_tab[i].pin;
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dir = qe_iop_conf_tab[i].dir;
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open_drain = qe_iop_conf_tab[i].open_drain;
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assign = qe_iop_conf_tab[i].assign;
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qe_config_iopin(port, pin, dir, open_drain, assign);
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}
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}
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#endif
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/*
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* Breathe some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f (volatile immap_t * im)
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{
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
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/* Clear initial global data */
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memset ((void *) gd, 0, sizeof (gd_t));
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/* system performance tweaking */
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#ifdef CFG_ACR_PIPE_DEP
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/* Arbiter pipeline depth */
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im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
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(CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
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#endif
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#ifdef CFG_ACR_RPTCNT
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/* Arbiter repeat count */
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im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
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(CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
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#endif
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#ifdef CFG_SPCR_OPT
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/* Optimize transactions between CSB and other devices */
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im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
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(CFG_SPCR_OPT << SPCR_OPT_SHIFT);
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#endif
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#ifdef CFG_SPCR_TSECEP
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/* all eTSEC's Emergency priority */
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im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) |
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(CFG_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
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#endif
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#ifdef CFG_SPCR_TSEC1EP
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/* TSEC1 Emergency priority */
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im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) |
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(CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
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#endif
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#ifdef CFG_SPCR_TSEC2EP
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/* TSEC2 Emergency priority */
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im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) |
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(CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
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#endif
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#ifdef CFG_SCCR_ENCCM
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/* Encryption clock mode */
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im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) |
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(CFG_SCCR_ENCCM << SCCR_PCICM_SHIFT);
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#endif
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#ifdef CFG_SCCR_PCICM
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/* PCI & DMA clock mode */
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im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) |
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(CFG_SCCR_PCICM << SCCR_PCICM_SHIFT);
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#endif
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#ifdef CFG_SCCR_TSECCM
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/* all TSEC's clock mode */
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im->clk.sccr = (im->clk.sccr & ~SCCR_TSECCM) |
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(CFG_SCCR_TSECCM << SCCR_TSECCM_SHIFT);
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#endif
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#ifdef CFG_SCCR_TSEC1CM
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/* TSEC1 clock mode */
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im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) |
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(CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
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#endif
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#ifdef CFG_SCCR_TSEC2CM
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/* TSEC2 clock mode */
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im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) |
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(CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
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#endif
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#ifdef CFG_SCCR_TSEC1ON
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/* TSEC1 clock switch */
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im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) |
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(CFG_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT);
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#endif
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#ifdef CFG_SCCR_TSEC2ON
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/* TSEC2 clock switch */
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im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) |
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(CFG_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT);
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#endif
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#ifdef CFG_SCCR_USBMPHCM
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/* USB MPH clock mode */
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im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) |
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(CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
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#endif
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#ifdef CFG_SCCR_USBDRCM
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/* USB DR clock mode */
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im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) |
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(CFG_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
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#endif
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#ifdef CFG_SCCR_SATACM
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/* SATA controller clock mode */
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im->clk.sccr = (im->clk.sccr & ~SCCR_SATACM) |
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(CFG_SCCR_SATACM << SCCR_SATACM_SHIFT);
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#endif
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/* RSR - Reset Status Register - clear all status (4.6.1.3) */
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gd->reset_status = im->reset.rsr;
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im->reset.rsr = ~(RSR_RES);
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/*
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* RMR - Reset Mode Register
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* contains checkstop reset enable (4.6.1.4)
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*/
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im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));
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/* LCRR - Clock Ratio Register (10.3.1.16) */
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im->lbus.lcrr = CFG_LCRR;
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/* Enable Time Base & Decrimenter ( so we will have udelay() )*/
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im->sysconf.spcr |= SPCR_TBEN;
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/* System General Purpose Register */
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#ifdef CFG_SICRH
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#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8313)
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/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
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im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CFG_SICRH;
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#else
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im->sysconf.sicrh = CFG_SICRH;
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#endif
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#endif
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#ifdef CFG_SICRL
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im->sysconf.sicrl = CFG_SICRL;
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#endif
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/* DDR control driver register */
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#ifdef CFG_DDRCDR
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im->sysconf.ddrcdr = CFG_DDRCDR;
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#endif
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/* Output buffer impedance register */
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#ifdef CFG_OBIR
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im->sysconf.obir = CFG_OBIR;
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#endif
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#ifdef CONFIG_QE
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/* Config QE ioports */
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config_qe_ioports();
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#endif
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/*
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* Memory Controller:
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*/
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/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
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* addresses - these have to be modified later when FLASH size
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* has been determined
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*/
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#if defined(CFG_BR0_PRELIM) \
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&& defined(CFG_OR0_PRELIM) \
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&& defined(CFG_LBLAWBAR0_PRELIM) \
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&& defined(CFG_LBLAWAR0_PRELIM)
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im->lbus.bank[0].br = CFG_BR0_PRELIM;
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im->lbus.bank[0].or = CFG_OR0_PRELIM;
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im->sysconf.lblaw[0].bar = CFG_LBLAWBAR0_PRELIM;
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im->sysconf.lblaw[0].ar = CFG_LBLAWAR0_PRELIM;
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#else
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#error CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined
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#endif
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#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
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im->lbus.bank[1].br = CFG_BR1_PRELIM;
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im->lbus.bank[1].or = CFG_OR1_PRELIM;
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#endif
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#if defined(CFG_LBLAWBAR1_PRELIM) && defined(CFG_LBLAWAR1_PRELIM)
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im->sysconf.lblaw[1].bar = CFG_LBLAWBAR1_PRELIM;
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im->sysconf.lblaw[1].ar = CFG_LBLAWAR1_PRELIM;
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#endif
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#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
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im->lbus.bank[2].br = CFG_BR2_PRELIM;
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im->lbus.bank[2].or = CFG_OR2_PRELIM;
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#endif
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#if defined(CFG_LBLAWBAR2_PRELIM) && defined(CFG_LBLAWAR2_PRELIM)
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im->sysconf.lblaw[2].bar = CFG_LBLAWBAR2_PRELIM;
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im->sysconf.lblaw[2].ar = CFG_LBLAWAR2_PRELIM;
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#endif
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#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
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im->lbus.bank[3].br = CFG_BR3_PRELIM;
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im->lbus.bank[3].or = CFG_OR3_PRELIM;
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#endif
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#if defined(CFG_LBLAWBAR3_PRELIM) && defined(CFG_LBLAWAR3_PRELIM)
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im->sysconf.lblaw[3].bar = CFG_LBLAWBAR3_PRELIM;
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im->sysconf.lblaw[3].ar = CFG_LBLAWAR3_PRELIM;
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#endif
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#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
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im->lbus.bank[4].br = CFG_BR4_PRELIM;
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im->lbus.bank[4].or = CFG_OR4_PRELIM;
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#endif
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#if defined(CFG_LBLAWBAR4_PRELIM) && defined(CFG_LBLAWAR4_PRELIM)
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im->sysconf.lblaw[4].bar = CFG_LBLAWBAR4_PRELIM;
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im->sysconf.lblaw[4].ar = CFG_LBLAWAR4_PRELIM;
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#endif
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#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
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im->lbus.bank[5].br = CFG_BR5_PRELIM;
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im->lbus.bank[5].or = CFG_OR5_PRELIM;
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#endif
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#if defined(CFG_LBLAWBAR5_PRELIM) && defined(CFG_LBLAWAR5_PRELIM)
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im->sysconf.lblaw[5].bar = CFG_LBLAWBAR5_PRELIM;
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im->sysconf.lblaw[5].ar = CFG_LBLAWAR5_PRELIM;
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#endif
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#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
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im->lbus.bank[6].br = CFG_BR6_PRELIM;
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im->lbus.bank[6].or = CFG_OR6_PRELIM;
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#endif
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#if defined(CFG_LBLAWBAR6_PRELIM) && defined(CFG_LBLAWAR6_PRELIM)
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im->sysconf.lblaw[6].bar = CFG_LBLAWBAR6_PRELIM;
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im->sysconf.lblaw[6].ar = CFG_LBLAWAR6_PRELIM;
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#endif
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#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
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im->lbus.bank[7].br = CFG_BR7_PRELIM;
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im->lbus.bank[7].or = CFG_OR7_PRELIM;
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#endif
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#if defined(CFG_LBLAWBAR7_PRELIM) && defined(CFG_LBLAWAR7_PRELIM)
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im->sysconf.lblaw[7].bar = CFG_LBLAWBAR7_PRELIM;
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im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
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#endif
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#ifdef CFG_GPIO1_PRELIM
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im->gpio[0].dat = CFG_GPIO1_DAT;
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im->gpio[0].dir = CFG_GPIO1_DIR;
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#endif
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#ifdef CFG_GPIO2_PRELIM
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im->gpio[1].dat = CFG_GPIO2_DAT;
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im->gpio[1].dir = CFG_GPIO2_DIR;
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#endif
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}
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int cpu_init_r (void)
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{
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#ifdef CONFIG_QE
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uint qe_base = CFG_IMMR + 0x00100000; /* QE immr base */
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qe_init(qe_base);
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qe_reset();
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#endif
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return 0;
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}
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/*
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* Figure out the cause of the reset
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*/
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int prt_83xx_rsr(void)
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{
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static struct {
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ulong mask;
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char *desc;
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} bits[] = {
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{
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RSR_SWSR, "Software Soft"}, {
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RSR_SWHR, "Software Hard"}, {
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RSR_JSRS, "JTAG Soft"}, {
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RSR_CSHR, "Check Stop"}, {
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RSR_SWRS, "Software Watchdog"}, {
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RSR_BMRS, "Bus Monitor"}, {
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RSR_SRS, "External/Internal Soft"}, {
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RSR_HRS, "External/Internal Hard"}
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};
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static int n = sizeof bits / sizeof bits[0];
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ulong rsr = gd->reset_status;
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int i;
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char *sep;
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puts("Reset Status:");
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sep = " ";
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for (i = 0; i < n; i++)
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if (rsr & bits[i].mask) {
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printf("%s%s", sep, bits[i].desc);
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sep = ", ";
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}
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puts("\n\n");
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return 0;
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}
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