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https://github.com/brain-hackers/u-boot-brain
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9f3183d2d6
There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
56 lines
788 B
C
56 lines
788 B
C
/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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#ifndef __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__
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#define __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__
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#define I2C_QUIRK_REG /* enable 8-bit driver */
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#ifdef CONFIG_FSL_LPUART
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#ifdef CONFIG_LPUART_32B_REG
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struct lpuart_fsl {
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u32 baud;
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u32 stat;
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u32 ctrl;
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u32 data;
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u32 match;
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u32 modir;
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u32 fifo;
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u32 water;
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};
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#else
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struct lpuart_fsl {
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u8 ubdh;
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u8 ubdl;
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u8 uc1;
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u8 uc2;
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u8 us1;
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u8 us2;
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u8 uc3;
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u8 ud;
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u8 uma1;
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u8 uma2;
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u8 uc4;
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u8 uc5;
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u8 ued;
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u8 umodem;
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u8 uir;
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u8 reserved;
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u8 upfifo;
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u8 ucfifo;
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u8 usfifo;
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u8 utwfifo;
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u8 utcfifo;
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u8 urwfifo;
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u8 urcfifo;
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u8 rsvd[28];
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};
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#endif
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#endif /* CONFIG_FSL_LPUART */
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#endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */
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