41 lines
849 B
C
41 lines
849 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_MT7620_CLK_H_
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#define _DT_BINDINGS_MT7620_CLK_H_
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/* Base clocks */
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#define CLK_SYS 34
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#define CLK_CPU 33
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#define CLK_XTAL 32
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/* Peripheral clocks */
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#define CLK_SDHC 30
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#define CLK_MIPS_CNT 28
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#define CLK_PCIE 26
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#define CLK_UPHY_12M 25
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#define CLK_EPHY 24
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#define CLK_ESW 23
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#define CLK_UPHY_48M 22
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#define CLK_FE 21
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#define CLK_UARTL 19
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#define CLK_SPI 18
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#define CLK_I2S 17
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#define CLK_I2C 16
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#define CLK_NAND 15
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#define CLK_GDMA 14
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#define CLK_PIO 13
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#define CLK_UARTF 12
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#define CLK_PCM 11
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#define CLK_MC 10
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#define CLK_INTC 9
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#define CLK_TIMER 8
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#define CLK_GE2 7
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#define CLK_GE1 6
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#endif /* _DT_BINDINGS_MT7620_CLK_H_ */
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