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https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 11:16:15 +09:00
cc32fd911a
The definition follows the DSA binding in kernel and describes the switch, its ports and PHYs. The switch node has the same structure as in Linux and this patch enables it (and relevant ports) for the LS1028A RDB board. ENETC PF6 is the 2nd Eth controller linked to the switch on LS1028A, it is not used in U-Boot and was disabled. Ethernet port aliases were also added to better manage the multitude of ports available now. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Michael Walle <michael@walle.cc>
204 lines
2.4 KiB
Plaintext
204 lines
2.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP ls1028ARDB device tree source
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*
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* Copyright 2019 NXP
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*
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*/
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/dts-v1/;
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#include "fsl-ls1028a.dtsi"
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/ {
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model = "NXP Layerscape 1028a RDB Board";
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compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
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aliases {
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spi0 = &fspi;
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eth0 = &enetc0;
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eth1 = &enetc2;
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eth2 = &mscc_felix_port0;
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eth3 = &mscc_felix_port1;
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eth4 = &mscc_felix_port2;
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eth5 = &mscc_felix_port3;
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};
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};
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&dspi0 {
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status = "okay";
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};
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&dspi1 {
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status = "okay";
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};
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&dspi2 {
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status = "okay";
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};
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&esdhc0 {
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status = "okay";
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};
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&esdhc1 {
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status = "okay";
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mmc-hs200-1_8v;
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};
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&fspi {
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status = "okay";
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mt35xu02g0: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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reg = <0>;
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spi-rx-bus-width = <8>;
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spi-tx-bus-width = <1>;
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};
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};
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&i2c0 {
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status = "okay";
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u-boot,dm-pre-reloc;
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i2c-mux@77 {
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compatible = "nxp,pca9547";
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reg = <0x77>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3>;
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rtc@51 {
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compatible = "pcf2127-rtc";
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reg = <0x51>;
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};
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};
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};
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};
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&i2c1 {
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status = "okay";
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};
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&i2c2 {
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status = "okay";
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};
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&i2c3 {
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status = "okay";
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};
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&i2c4 {
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status = "okay";
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};
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&i2c5 {
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status = "okay";
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};
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&i2c6 {
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status = "okay";
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};
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&i2c7 {
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status = "okay";
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};
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&sata {
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status = "okay";
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};
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&serial0 {
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status = "okay";
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};
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&serial1 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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&usb2 {
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status = "okay";
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};
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&enetc0 {
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status = "okay";
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phy-mode = "sgmii";
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phy-handle = <&rdb_phy0>;
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};
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&enetc2 {
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status = "okay";
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};
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&mscc_felix {
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status = "okay";
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};
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&mscc_felix_port0 {
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label = "swp0";
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phy-handle = <&sw_phy0>;
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phy-mode = "qsgmii";
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status = "okay";
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};
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&mscc_felix_port1 {
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label = "swp1";
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phy-handle = <&sw_phy1>;
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phy-mode = "qsgmii";
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status = "okay";
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};
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&mscc_felix_port2 {
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label = "swp2";
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phy-handle = <&sw_phy2>;
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phy-mode = "qsgmii";
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status = "okay";
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};
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&mscc_felix_port3 {
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label = "swp3";
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phy-handle = <&sw_phy3>;
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phy-mode = "qsgmii";
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status = "okay";
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};
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&mscc_felix_port4 {
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ethernet = <&enetc2>;
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status = "okay";
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};
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&mdio0 {
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status = "okay";
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rdb_phy0: phy@2 {
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reg = <2>;
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};
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/* VSC8514 QSGMII PHY */
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sw_phy0: phy@10 {
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reg = <0x10>;
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};
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sw_phy1: phy@11 {
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reg = <0x11>;
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};
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sw_phy2: phy@12 {
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reg = <0x12>;
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};
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sw_phy3: phy@13 {
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reg = <0x13>;
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};
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};
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