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https://github.com/brain-hackers/u-boot-brain
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611a28ce27
The System Control Unit (SCU) controller of Aspeed SoCs provides the reset control for each peripheral. This patch refactors the reset method to leverage the SCU reset control. Thus the driver dependency on watchdog including dedicated WDT API and reset flag encoding can be eliminated. The Kconfig description is also updated accordingly. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
89 lines
1.6 KiB
Plaintext
89 lines
1.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/clock/aspeed-clock.h>
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#include <dt-bindings/reset/ast2500-reset.h>
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#include "ast2500.dtsi"
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/ {
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scu: clock-controller@1e6e2000 {
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compatible = "aspeed,ast2500-scu";
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reg = <0x1e6e2000 0x1000>;
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u-boot,dm-pre-reloc;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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rst: reset-controller {
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u-boot,dm-pre-reloc;
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compatible = "aspeed,ast2500-reset";
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#reset-cells = <1>;
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};
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sdrammc: sdrammc@1e6e0000 {
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u-boot,dm-pre-reloc;
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compatible = "aspeed,ast2500-sdrammc";
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reg = <0x1e6e0000 0x174
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0x1e6e0200 0x1d4 >;
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#reset-cells = <1>;
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clocks = <&scu ASPEED_CLK_MPLL>;
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resets = <&rst ASPEED_RESET_SDRAM>;
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};
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ahb {
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u-boot,dm-pre-reloc;
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apb {
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u-boot,dm-pre-reloc;
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sdhci0: sdhci@1e740100 {
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compatible = "aspeed,ast2500-sdhci";
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reg = <0x1e740100>;
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#reset-cells = <1>;
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clocks = <&scu ASPEED_CLK_SDIO>;
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resets = <&rst ASPEED_RESET_SDIO>;
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};
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sdhci1: sdhci@1e740200 {
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compatible = "aspeed,ast2500-sdhci";
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reg = <0x1e740200>;
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#reset-cells = <1>;
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clocks = <&scu ASPEED_CLK_SDIO>;
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resets = <&rst ASPEED_RESET_SDIO>;
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};
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};
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};
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};
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&uart1 {
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clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
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};
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&uart2 {
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clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
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};
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&uart3 {
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clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
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};
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&uart4 {
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clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
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};
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&uart5 {
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clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
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};
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&timer {
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u-boot,dm-pre-reloc;
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};
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&mac0 {
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clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
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};
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&mac1 {
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clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
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};
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