Tom Warren d94c2dbd0a Tegra: Fix MSELECT clock divisors for T30/T114. ... A comparison of registers between our internal NV U-Boot and u-boot-tegra/next showed some discrepancies in the MSELECT clock divisor programming. T20 doesn't have a MSELECT clk src reg. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>		2013-04-15 11:01:38 -07:00
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cpu	Tegra: Fix MSELECT clock divisors for T30/T114.	2013-04-15 11:01:38 -07:00
dts	EXYNOS5: Add device node for DP	2013-03-27 21:23:18 +09:00
imx-common	imx: Add u-boot-with-nand-spl.imx make target	2013-04-12 07:55:08 +02:00
include/asm	Tegra114: Initialize System Counter (TSC) with osc frequency	2013-04-15 11:01:38 -07:00
lib	arm: Remove deprecated and now unused NAND SPL	2013-04-12 07:55:08 +02:00
config.mk	arm: Remove deprecated and now unused NAND SPL	2013-04-12 07:55:08 +02:00