mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-10 05:06:16 +09:00
d93d0f0cfe
This patch is intended to prepare the other S5P SoC. (s5pc210) If use SoC specific defines then can't share with other SoC. So, make the accessor functions for access the base address by common way. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
216 lines
4.5 KiB
ArmAsm
216 lines
4.5 KiB
ArmAsm
/*
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* Copyright (C) 2009 Samsung Electronics
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* Kyungmin Park <kyungmin.park@samsung.com>
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* Minkyu Kang <mk7.kang@samsung.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/power.h>
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/*
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* Register usages:
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*
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* r5 has zero always
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*/
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_TEXT_BASE:
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.word TEXT_BASE
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.globl lowlevel_init
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lowlevel_init:
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mov r9, lr
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/* r5 has always zero */
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mov r5, #0
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ldr r8, =S5PC100_GPIO_BASE
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/* Disable Watchdog */
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ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
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orr r0, r0, #0x0
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str r5, [r0]
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#ifndef CONFIG_ONENAND_IPL
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/* setting SRAM */
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ldr r0, =S5PC100_SROMC_BASE
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ldr r1, =0x9
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str r1, [r0]
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#endif
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/* S5PC100 has 3 groups of interrupt sources */
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ldr r0, =S5PC100_VIC0_BASE @0xE4000000
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ldr r1, =S5PC100_VIC1_BASE @0xE4000000
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ldr r2, =S5PC100_VIC2_BASE @0xE4000000
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/* Disable all interrupts (VIC0, VIC1 and VIC2) */
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mvn r3, #0x0
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str r3, [r0, #0x14] @INTENCLEAR
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str r3, [r1, #0x14] @INTENCLEAR
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str r3, [r2, #0x14] @INTENCLEAR
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#ifndef CONFIG_ONENAND_IPL
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/* Set all interrupts as IRQ */
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str r5, [r0, #0xc] @INTSELECT
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str r5, [r1, #0xc] @INTSELECT
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str r5, [r2, #0xc] @INTSELECT
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/* Pending Interrupt Clear */
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str r5, [r0, #0xf00] @INTADDRESS
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str r5, [r1, #0xf00] @INTADDRESS
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str r5, [r2, #0xf00] @INTADDRESS
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#endif
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#ifndef CONFIG_ONENAND_IPL
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/* for UART */
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bl uart_asm_init
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/* for TZPC */
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bl tzpc_asm_init
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#endif
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#ifdef CONFIG_ONENAND_IPL
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/* init system clock */
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bl system_clock_init
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bl mem_ctrl_asm_init
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/* Wakeup support. Don't know if it's going to be used, untested. */
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ldr r0, =S5PC100_RST_STAT
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ldr r1, [r0]
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bic r1, r1, #0xfffffff7
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cmp r1, #0x8
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beq wakeup_reset
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#endif
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1:
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mov lr, r9
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mov pc, lr
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#ifdef CONFIG_ONENAND_IPL
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wakeup_reset:
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/* Clear wakeup status register */
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ldr r0, =S5PC100_WAKEUP_STAT
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ldr r1, [r0]
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str r1, [r0]
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/* Load return address and jump to kernel */
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ldr r0, =S5PC100_INFORM0
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/* r1 = physical address of s5pc100_cpu_resume function */
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ldr r1, [r0]
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/* Jump to kernel (sleep.S) */
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mov pc, r1
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nop
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nop
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#endif
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/*
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* system_clock_init: Initialize core clock and bus clock.
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* void system_clock_init(void)
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*/
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system_clock_init:
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ldr r8, =S5PC100_CLOCK_BASE @ 0xE0100000
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/* Set Clock divider */
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ldr r1, =0x00011110
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str r1, [r8, #0x304]
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ldr r1, =0x1
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str r1, [r8, #0x308]
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ldr r1, =0x00011301
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str r1, [r8, #0x300]
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/* Set Lock Time */
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ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
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str r1, [r8, #0x000] @ APLL_LOCK
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str r1, [r8, #0x004] @ MPLL_LOCK
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str r1, [r8, #0x008] @ EPLL_LOCK
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str r1, [r8, #0x00C] @ HPLL_LOCK
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/* APLL_CON */
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ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
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str r1, [r8, #0x100]
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/* MPLL_CON */
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ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
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str r1, [r8, #0x104]
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/* EPLL_CON */
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ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
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str r1, [r8, #0x108]
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/* HPLL_CON */
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ldr r1, =0x80600603
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str r1, [r8, #0x10C]
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/* Set Source Clock */
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ldr r1, =0x1111 @ A, M, E, HPLL Muxing
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str r1, [r8, #0x200] @ CLK_SRC0
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ldr r1, =0x1000001 @ Uart Clock & CLK48M Muxing
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str r1, [r8, #0x204] @ CLK_SRC1
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ldr r1, =0x9000 @ ARMCLK/4
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str r1, [r8, #0x400] @ CLK_OUT
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/* wait at least 200us to stablize all clock */
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mov r2, #0x10000
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1: subs r2, r2, #1
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bne 1b
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mov pc, lr
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#ifndef CONFIG_ONENAND_IPL
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/*
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* uart_asm_init: Initialize UART's pins
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*/
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uart_asm_init:
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mov r0, r8
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ldr r1, =0x22222222
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str r1, [r0, #0x0] @ GPA0_CON
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ldr r1, =0x00022222
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str r1, [r0, #0x20] @ GPA1_CON
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mov pc, lr
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/*
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* tzpc_asm_init: Initialize TZPC
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*/
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tzpc_asm_init:
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ldr r0, =0xE3800000
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mov r1, #0x0
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str r1, [r0]
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mov r1, #0xff
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str r1, [r0, #0x804]
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str r1, [r0, #0x810]
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ldr r0, =0xE2800000
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str r1, [r0, #0x804]
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str r1, [r0, #0x810]
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str r1, [r0, #0x81C]
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ldr r0, =0xE2900000
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str r1, [r0, #0x804]
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str r1, [r0, #0x810]
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mov pc, lr
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#endif
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