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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass <sjg@chromium.org>
252 lines
6.3 KiB
C
252 lines
6.3 KiB
C
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* (C) Copyright 2008
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* Graeme Russ, graeme.russ@gmail.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/ibmpc.h>
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#ifndef __CONFIG_X86_COMMON_H
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#define __CONFIG_X86_COMMON_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_SHOW_BOOT_PROGRESS
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#define CONFIG_SYS_VSNPRINTF
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#define CONFIG_ZBOOT_32
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#define CONFIG_PHYSMEM
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#define CONFIG_DISPLAY_BOARDINFO_LATE
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DM
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#define CONFIG_CMD_DM
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#define CONFIG_DM_GPIO
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#define CONFIG_DM_SERIAL
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#define CONFIG_LMB
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#define CONFIG_OF_LIBFDT
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#define CONFIG_LZO
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#define CONFIG_FIT
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#undef CONFIG_ZLIB
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#undef CONFIG_GZIP
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#define CONFIG_SYS_BOOTM_LEN (16 << 20)
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/* SATA AHCI storage */
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#define CONFIG_SCSI_AHCI
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#define CONFIG_SATA_INTEL
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#ifdef CONFIG_SCSI_AHCI
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#define CONFIG_LIBATA
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#define CONFIG_SYS_64BIT_LBA
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#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
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#define CONFIG_SYS_SCSI_MAX_LUN 1
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#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
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CONFIG_SYS_SCSI_MAX_LUN)
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#endif
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/* Generic TPM interfaced through LPC bus */
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#define CONFIG_TPM
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#define CONFIG_TPM_TIS_LPC
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#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000
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/*-----------------------------------------------------------------------
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* Real Time Clock Configuration
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*/
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#define CONFIG_RTC_MC146818
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#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
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#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS
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/*-----------------------------------------------------------------------
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* Serial Configuration
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*/
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#define CONFIG_SYS_NS16550
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
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9600, 19200, 38400, 115200}
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#define CONFIG_SYS_NS16550_PORT_MAPPED
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#define CONFIG_CONSOLE_MUX
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#define CONFIG_SYS_STDIO_DEREGISTER
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_COMMAND_HISTORY
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SUPPORT_VFAT
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/************************************************************
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* ATAPI support (experimental)
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************************************************************/
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#define CONFIG_ATAPI
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/************************************************************
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* DISK Partition support
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************************************************************/
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#define CONFIG_EFI_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_MAC_PARTITION
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#define CONFIG_ISO_PARTITION /* Experimental */
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#define CONFIG_CMD_PART
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#define CONFIG_CMD_CBFS
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#define CONFIG_CMD_EXT4
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#define CONFIG_CMD_EXT4_WRITE
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#define CONFIG_PARTITION_UUIDS
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#define CONFIG_SYS_CONSOLE_INFO_QUIET
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/* x86 GPIOs are accessed through a PCI device */
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#define CONFIG_INTEL_ICH6_GPIO
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/*-----------------------------------------------------------------------
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BDI
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#define CONFIG_CMD_BOOTD
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#define CONFIG_CMD_CONSOLE
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_ECHO
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#undef CONFIG_CMD_FLASH
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#define CONFIG_CMD_FPGA
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#define CONFIG_CMD_FPGA_LOADMK
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#define CONFIG_CMD_GPIO
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#define CONFIG_CMD_IMI
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#undef CONFIG_CMD_IMLS
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#define CONFIG_CMD_IO
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_ITEST
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#define CONFIG_CMD_LOADB
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#define CONFIG_CMD_LOADS
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_MISC
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#define CONFIG_CMD_NET
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#undef CONFIG_CMD_NFS
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_RUN
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_SETGETDCR
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#define CONFIG_CMD_SOURCE
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#define CONFIG_CMD_TIME
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#define CONFIG_CMD_GETTIME
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#define CONFIG_CMD_XIMG
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#define CONFIG_CMD_SCSI
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_ZBOOT
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#define CONFIG_CMD_ELF
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#define CONFIG_BOOTARGS \
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"root=/dev/sdb3 init=/sbin/init rootwait ro"
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#define CONFIG_BOOTCOMMAND \
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"ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 115200
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_CBSIZE 512
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + \
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16)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_MEMTEST_START 0x00100000
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#define CONFIG_SYS_MEMTEST_END 0x01000000
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#define CONFIG_SYS_LOAD_ADDR 0x20000000
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/*-----------------------------------------------------------------------
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* Video Configuration
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*/
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#define CONFIG_VIDEO
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#define CONFIG_VIDEO_SW_CURSOR
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#define VIDEO_FB_16BPP_WORD_SWAP
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#define CONFIG_I8042_KBD
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#define CONFIG_CFB_CONSOLE
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/*-----------------------------------------------------------------------
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* CPU Features
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*/
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#define CONFIG_SYS_X86_TSC_TIMER
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#define CONFIG_SYS_PCAT_INTERRUPTS
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#define CONFIG_SYS_PCAT_TIMER
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#define CONFIG_SYS_NUM_IRQS 16
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#define CONFIG_SYS_STACK_SIZE (32 * 1024)
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MALLOC_LEN 0x200000
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#define CONFIG_SYS_MALLOC_F_LEN (2 << 10)
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/*-----------------------------------------------------------------------
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* FLASH configuration
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*/
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#define CONFIG_ICH_SPI
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_MACRONIX
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#define CONFIG_SPI_FLASH_WINBOND
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#define CONFIG_SPI_FLASH_GIGADEVICE
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_CMD_SF
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#define CONFIG_CMD_SF_TEST
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#define CONFIG_CMD_SPI
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#define CONFIG_SPI
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/*-----------------------------------------------------------------------
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* Environment configuration
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*/
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#define CONFIG_ENV_IS_NOWHERE
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#define CONFIG_ENV_SIZE 0x01000
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/*-----------------------------------------------------------------------
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* PCI configuration
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*/
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#define CONFIG_PCI
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/*-----------------------------------------------------------------------
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* USB configuration
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*/
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_PCI
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#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_USB_STORAGE
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#define CONFIG_USB_KEYBOARD
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#define CONFIG_SYS_USB_EVENT_POLL
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#define CONFIG_USB_HOST_ETHER
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#define CONFIG_USB_ETHER_ASIX
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#define CONFIG_USB_ETHER_SMSC95XX
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#define CONFIG_TFTP_TSIZE
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#define CONFIG_CMD_DHCP
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_CMD_USB
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_STD_DEVICES_SETTINGS
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#endif /* __CONFIG_H */
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