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https://github.com/brain-hackers/u-boot-brain
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bf4ea7ed21
Don't just define ARCH_DMA_MINALIGN but also CONFIG_SYS_CACHELINE_SIZE if it's undefined. This is needed for the xhci driver to compile. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
37 lines
715 B
C
37 lines
715 B
C
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __X86_CACHE_H__
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#define __X86_CACHE_H__
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/*
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* If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise
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* use 64-bytes, a safe default for x86.
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*/
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#ifndef CONFIG_SYS_CACHELINE_SIZE
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#define CONFIG_SYS_CACHELINE_SIZE 64
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#endif
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#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
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static inline void wbinvd(void)
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{
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asm volatile ("wbinvd" : : : "memory");
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}
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static inline void invd(void)
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{
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asm volatile("invd" : : : "memory");
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}
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/* Enable caches and write buffer */
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void enable_caches(void);
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/* Disable caches and write buffer */
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void disable_caches(void);
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#endif /* __X86_CACHE_H__ */
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