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Parthiban Nallathambi d8d33b6d4d imx: Add variscite DART-6UL Evaluation Kit

Port for the DART-6UL Evaluation Kit SBC. Based on the variscite
DART-6UL iMX6ULL SoM.

CPU:   Freescale i.MX6ULL rev1.1 900 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 43C
Reset cause: POR
Model: Variscite DART-6UL Evaluation Kit
Board: Variscite DART-6UL Evaluation Kit
DRAM:  512 MiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:    serial@02020000
Out:   serial@02020000
Err:   serial@02020000
Net:   FEC0

Working:
 - Eth0
 - i2c
 - MMC/SD
 - eMMC
 - USB host
 - UART 1

Note: LCDIF porting needs DM_VIDEO
https://lists.denx.de/pipermail/u-boot/2019-April/365506.html

Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com>

2019-04-25 19:16:24 +02:00

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Raw Blame History

 MX6UL_DART BOARD
 M:	Parthiban Nallathambi <parthitce@gmail.com>
 S:	Maintained
 F:	arch/arm/dts/imx6ull-dart-6ul.dts
 F:	arch/arm/dts/imx6ull-dart-6ul.dtsi
 F:	board/variscite/dart_6ul/
 F:	configs/variscite_dart6ul_defconfig
 F:	include/configs/dart_6ul.h