mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 18:56:15 +09:00
d8b1d22512
Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31), which is just the same one found in other x86 chipset. Since we programmed the GPIO register block base address, we should be able to enable the GPIO support on Intel Galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
83 lines
1.6 KiB
Plaintext
83 lines
1.6 KiB
Plaintext
/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include <dt-bindings/mrc/quark.h>
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/include/ "skeleton.dtsi"
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/ {
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model = "Intel Galileo";
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compatible = "intel,galileo", "intel,quark";
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config {
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silent_console = <0>;
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};
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chosen {
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stdout-path = &pciuart0;
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};
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mrc {
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compatible = "intel,quark-mrc";
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flags = <MRC_FLAG_SCRAMBLE_EN>;
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dram-width = <DRAM_WIDTH_X8>;
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dram-speed = <DRAM_FREQ_800>;
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dram-type = <DRAM_TYPE_DDR3>;
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rank-mask = <DRAM_RANK(0)>;
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chan-mask = <DRAM_CHANNEL(0)>;
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chan-width = <DRAM_CHANNEL_WIDTH_X16>;
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addr-mode = <DRAM_ADDR_MODE0>;
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refresh-rate = <DRAM_REFRESH_RATE_785US>;
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sr-temp-range = <DRAM_SRT_RANGE_NORMAL>;
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ron-value = <DRAM_RON_34OHM>;
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rtt-nom-value = <DRAM_RTT_NOM_120OHM>;
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rd-odt-value = <DRAM_RD_ODT_OFF>;
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dram-density = <DRAM_DENSITY_1G>;
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dram-cl = <6>;
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dram-ras = <0x0000927c>;
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dram-wtr = <0x00002710>;
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dram-rrd = <0x00002710>;
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dram-faw = <0x00009c40>;
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};
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pci {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "intel,pci";
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device_type = "pci";
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pciuart0: uart@14,5 {
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compatible = "pci8086,0936.00",
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"pci8086,0936",
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"pciclass,070002",
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"pciclass,0700",
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"x86-uart";
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reg = <0x0000a500 0x0 0x0 0x0 0x0
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0x0200a510 0x0 0x0 0x0 0x0>;
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reg-shift = <2>;
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clock-frequency = <44236800>;
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current-speed = <115200>;
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};
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};
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gpioa {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0 0x20>;
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bank-name = "A";
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};
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gpiob {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x20 0x20>;
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bank-name = "B";
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};
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};
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