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![]() GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
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am43xx | ||
am335x | ||
am3517crane | ||
beagle | ||
dra7xx | ||
evm | ||
omap5_uevm | ||
omap5912osk | ||
panda | ||
sdp3430 | ||
sdp4430 | ||
ti814x | ||
ti816x | ||
tnetv107xevm |