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https://github.com/brain-hackers/u-boot-brain
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d7e1f02efc
The peach boards have their SDRAM start address at 0x20000000 instead of 0x40000000 which seems common for all other exynos5 based boards. This means the layout set in exynos5-common.h causes the kernel be loaded more then 128MB (at 0x42000000) away from memory start which breaks booting kernels with CONFIG_AUTO_ZRELADDR Define a custom MEM_LAYOUT_ENV_SETTINGS for both peach boards which uses the same offsets from start of memory as the common exynos5 settings. This fixes booting via bootz and PXE Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
63 lines
1.5 KiB
C
63 lines
1.5 KiB
C
/*
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* Copyright (C) 2014 Samsung Electronics
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*
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* Configuration settings for the SAMSUNG/GOOGLE PEACH-PI board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_PEACH_PI_H
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#define __CONFIG_PEACH_PI_H
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_SPI_FLASH
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#define CONFIG_ENV_SPI_BASE 0x12D30000
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#define FLASH_SIZE (0x4 << 20)
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#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
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#define CONFIG_SPI_BOOTING
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#define MEM_LAYOUT_ENV_SETTINGS \
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"bootm_size=0x10000000\0" \
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"kernel_addr_r=0x22000000\0" \
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"fdt_addr_r=0x23000000\0" \
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"ramdisk_addr_r=0x23300000\0" \
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"scriptaddr=0x30000000\0" \
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"pxefile_addr_r=0x31000000\0"
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#include <configs/exynos5420-common.h>
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#include <configs/exynos5-dt-common.h>
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#define CONFIG_BOARD_COMMON
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_TEXT_BASE 0x23E00000
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800)
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/* select serial console configuration */
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#define CONFIG_SERIAL3 /* use SERIAL 3 */
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#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
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#define CONFIG_SYS_PROMPT "Peach-Pi # "
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#define CONFIG_IDENT_STRING " for Peach-Pi"
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#define CONFIG_VIDEO_PARADE
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/* Display */
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#define CONFIG_LCD
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#ifdef CONFIG_LCD
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#define CONFIG_EXYNOS_FB
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#define CONFIG_EXYNOS_DP
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#define LCD_BPP LCD_COLOR16
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#endif
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#define CONFIG_POWER_TPS65090_EC
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#define CONFIG_USB_XHCI
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#define CONFIG_USB_XHCI_EXYNOS
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/* DRAM Memory Banks */
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#define CONFIG_NR_DRAM_BANKS 7
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#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
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#endif /* __CONFIG_PEACH_PI_H */
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