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https://github.com/brain-hackers/u-boot-brain
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3fef31a392
To enable access to the slave CP its memory needs to be added to the MMU memory map. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
73 lines
1.5 KiB
C
73 lines
1.5 KiB
C
/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <libfdt.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/armv8/mmu.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Armada 7k/8k */
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#define MVEBU_RFU_BASE (MVEBU_REGISTER(0x6f0000))
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#define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84)
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#define RFU_SW_RESET_OFFSET 0
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static struct mm_region mvebu_mem_map[] = {
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{
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/* RAM */
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.phys = 0x0UL,
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.virt = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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},
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{
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/* SRAM, MMIO regions - AP806 region */
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.phys = 0xf0000000UL,
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.virt = 0xf0000000UL,
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.size = 0x01000000UL, /* 16MiB internal registers */
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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},
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{
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/* SRAM, MMIO regions - CP110 master region */
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.phys = 0xf2000000UL,
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.virt = 0xf2000000UL,
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.size = 0x02000000UL, /* 32MiB internal registers */
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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},
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{
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/* SRAM, MMIO regions - CP110 slave region */
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.phys = 0xf4000000UL,
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.virt = 0xf4000000UL,
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.size = 0x02000000UL, /* 32MiB internal registers */
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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},
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{
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = mvebu_mem_map;
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void reset_cpu(ulong ignored)
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{
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u32 reg;
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reg = readl(RFU_GLOBAL_SW_RST);
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reg &= ~(1 << RFU_SW_RESET_OFFSET);
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writel(reg, RFU_GLOBAL_SW_RST);
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}
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