mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 20:56:16 +09:00
d024236e5a
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
109 lines
2.7 KiB
C
109 lines
2.7 KiB
C
/*
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* Synopsys HSDK SDP Generic PLL clock driver
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*
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* Copyright (C) 2017 Synopsys
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* Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <asm-generic/gpio.h>
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#include <asm/io.h>
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <linux/printk.h>
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#define HSDK_CREG_MAX_GPIO 8
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#define GPIO_ACTIVATE 0x2
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#define GPIO_DEACTIVATE 0x3
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#define GPIO_PIN_MASK 0x3
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#define BIT_PER_GPIO 2
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struct hsdk_creg_gpio {
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uint32_t *regs;
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};
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static int hsdk_creg_gpio_set_value(struct udevice *dev, unsigned oft, int val)
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{
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struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
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uint32_t reg = readl(hcg->regs);
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uint32_t cmd = val ? GPIO_DEACTIVATE : GPIO_ACTIVATE;
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reg &= ~(GPIO_PIN_MASK << (oft * BIT_PER_GPIO));
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reg |= (cmd << (oft * BIT_PER_GPIO));
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writel(reg, hcg->regs);
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return 0;
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}
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static int hsdk_creg_gpio_direction_output(struct udevice *dev, unsigned oft,
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int val)
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{
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hsdk_creg_gpio_set_value(dev, oft, val);
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return 0;
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}
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static int hsdk_creg_gpio_direction_input(struct udevice *dev, unsigned oft)
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{
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pr_err("hsdk-creg-gpio can't be used as input!\n");
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return -ENOTSUPP;
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}
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static int hsdk_creg_gpio_get_value(struct udevice *dev, unsigned int oft)
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{
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struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
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uint32_t val = readl(hcg->regs);
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val = (val >> (oft * BIT_PER_GPIO)) & GPIO_PIN_MASK;
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return (val == GPIO_DEACTIVATE) ? 1 : 0;
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}
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static const struct dm_gpio_ops hsdk_creg_gpio_ops = {
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.direction_output = hsdk_creg_gpio_direction_output,
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.direction_input = hsdk_creg_gpio_direction_input,
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.set_value = hsdk_creg_gpio_set_value,
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.get_value = hsdk_creg_gpio_get_value,
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};
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static int hsdk_creg_gpio_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
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hcg->regs = (uint32_t *)devfdt_get_addr_ptr(dev);
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uc_priv->gpio_count = dev_read_u32_default(dev, "gpio-count", 1);
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if (uc_priv->gpio_count > HSDK_CREG_MAX_GPIO)
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uc_priv->gpio_count = HSDK_CREG_MAX_GPIO;
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uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
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if (!uc_priv->bank_name)
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uc_priv->bank_name = dev_read_name(dev);
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pr_debug("%s GPIO [0x%p] controller with %d gpios probed\n",
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uc_priv->bank_name, hcg->regs, uc_priv->gpio_count);
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return 0;
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}
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static const struct udevice_id hsdk_creg_gpio_ids[] = {
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{ .compatible = "snps,hsdk-creg-gpio" },
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{ }
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};
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U_BOOT_DRIVER(gpio_hsdk_creg) = {
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.name = "gpio_hsdk_creg",
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.id = UCLASS_GPIO,
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.ops = &hsdk_creg_gpio_ops,
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.probe = hsdk_creg_gpio_probe,
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.of_match = hsdk_creg_gpio_ids,
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.platdata_auto_alloc_size = sizeof(struct hsdk_creg_gpio),
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};
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