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https://github.com/brain-hackers/u-boot-brain
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4dbe4b168b
Since some driver like ohci, lcd used dcache functions. But m68k don't implement the invalidate_dcache_range()/flush_dcache_range() functions. To avoid compiling errors this patch adds an weak empty stub function for all m68k cpu. Also each cpu can implement its own implementation. If not implemented then by default is using an empty function. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Angelo Dureghello <angelo@sysam.it>
144 lines
3.4 KiB
C
144 lines
3.4 KiB
C
/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/immap.h>
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#include <asm/cache.h>
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volatile int *cf_icache_status = (int *)ICACHE_STATUS;
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volatile int *cf_dcache_status = (int *)DCACHE_STATUS;
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void flush_cache(ulong start_addr, ulong size)
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{
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/* Must be implemented for all M68k processors with copy-back data cache */
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}
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int icache_status(void)
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{
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return *cf_icache_status;
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}
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int dcache_status(void)
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{
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return *cf_dcache_status;
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}
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void icache_enable(void)
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{
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icache_invalid();
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*cf_icache_status = 1;
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#ifdef CONFIG_CF_V4
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__asm__ __volatile__("movec %0, %%acr2"::"r"(CONFIG_SYS_CACHE_ACR2));
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__asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3));
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#elif defined(CONFIG_CF_V4e)
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__asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6));
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__asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7));
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#else
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__asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
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__asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
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#endif
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__asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_ICACR));
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}
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void icache_disable(void)
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{
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u32 temp = 0;
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*cf_icache_status = 0;
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icache_invalid();
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#ifdef CONFIG_CF_V4
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__asm__ __volatile__("movec %0, %%acr2"::"r"(temp));
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__asm__ __volatile__("movec %0, %%acr3"::"r"(temp));
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#elif defined(CONFIG_CF_V4e)
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__asm__ __volatile__("movec %0, %%acr6"::"r"(temp));
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__asm__ __volatile__("movec %0, %%acr7"::"r"(temp));
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#else
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__asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
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__asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
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#endif
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}
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void icache_invalid(void)
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{
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u32 temp;
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temp = CONFIG_SYS_ICACHE_INV;
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if (*cf_icache_status)
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temp |= CONFIG_SYS_CACHE_ICACR;
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__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
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}
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/*
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* data cache only for ColdFire V4 such as MCF547x_8x, MCF5445x
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* the dcache will be dummy in ColdFire V2 and V3
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*/
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void dcache_enable(void)
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{
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dcache_invalid();
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*cf_dcache_status = 1;
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#ifdef CONFIG_CF_V4
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__asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
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__asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
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#elif defined(CONFIG_CF_V4e)
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__asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4));
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__asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5));
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#endif
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__asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_DCACR));
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}
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void dcache_disable(void)
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{
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u32 temp = 0;
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*cf_dcache_status = 0;
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dcache_invalid();
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__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
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#ifdef CONFIG_CF_V4
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__asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
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__asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
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#elif defined(CONFIG_CF_V4e)
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__asm__ __volatile__("movec %0, %%acr4"::"r"(temp));
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__asm__ __volatile__("movec %0, %%acr5"::"r"(temp));
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#endif
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}
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void dcache_invalid(void)
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{
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#ifdef CONFIG_CF_V4
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u32 temp;
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temp = CONFIG_SYS_DCACHE_INV;
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if (*cf_dcache_status)
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temp |= CONFIG_SYS_CACHE_DCACR;
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if (*cf_icache_status)
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temp |= CONFIG_SYS_CACHE_ICACR;
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__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
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#endif
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}
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__weak void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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/* An empty stub, real implementation should be in platform code */
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}
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__weak void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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/* An empty stub, real implementation should be in platform code */
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}
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