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![Liu Gang](/assets/img/avatar_default.png)
When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Slave's ucode and ENV can be stored in master's memory space, then slave can fetch them through PCIE interface. For the corenet platform, ucode is for Fman. NOTE: Because the slave can not erase, write master's NOR flash by PCIE interface, so it can not modify the ENV parameters stored in master's NOR flash using "saveenv" or other commands. environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Put the slave's ucode and ENV into it's own memory space. 4. Normally boot from local NOR flash. 5. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the slave module, need to finish these processes: 1. Set the boot location to one PCIE interface by RCW. 2. Set a specific TLB entry for the boot process. 3. Set a LAW entry with the TargetID of one PCIE for the boot. 4. Set a specific TLB entry in order to fetch ucode and ENV from master. 5. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 6. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. In addition, the processes are very similar between boot from SRIO and boot from PCIE. Some configurations like the address spaces can be set to the same. So the module of boot from PCIE was added based on the existing module of boot from SRIO, and the following changes were needed: 1. Updated the README.srio-boot-corenet to add descriptions about boot from PCIE, and change the name to README.srio-pcie-boot-corenet. 2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to "xxxx_SRIO_PCIE_BOOT", and the image builded with "xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and from PCIE. 3. Updated other macros and documents if needed to add information about boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
334 lines
7.7 KiB
C
334 lines
7.7 KiB
C
/*
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <linux/compiler.h>
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#include <asm/fsl_law.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS
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#ifdef CONFIG_FSL_CORENET
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#define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR)
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#define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar)
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#define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh)
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#define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl)
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#define LAWBAR_SHIFT 0
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#else
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#define LAW_BASE (CONFIG_SYS_IMMR + 0xc08)
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#define LAWAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x + 2)
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#define LAWBAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x)
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#define LAWBAR_SHIFT 12
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#endif
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static inline phys_addr_t get_law_base_addr(int idx)
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{
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#ifdef CONFIG_FSL_CORENET
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return (phys_addr_t)
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((u64)in_be32(LAWBARH_ADDR(idx)) << 32) |
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in_be32(LAWBARL_ADDR(idx));
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#else
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return (phys_addr_t)in_be32(LAWBAR_ADDR(idx)) << LAWBAR_SHIFT;
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#endif
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}
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static inline void set_law_base_addr(int idx, phys_addr_t addr)
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{
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#ifdef CONFIG_FSL_CORENET
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out_be32(LAWBARL_ADDR(idx), addr & 0xffffffff);
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out_be32(LAWBARH_ADDR(idx), (u64)addr >> 32);
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#else
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out_be32(LAWBAR_ADDR(idx), addr >> LAWBAR_SHIFT);
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#endif
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}
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void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
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{
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gd->used_laws |= (1 << idx);
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out_be32(LAWAR_ADDR(idx), 0);
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set_law_base_addr(idx, addr);
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out_be32(LAWAR_ADDR(idx), LAW_EN | ((u32)id << 20) | (u32)sz);
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/* Read back so that we sync the writes */
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in_be32(LAWAR_ADDR(idx));
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}
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void disable_law(u8 idx)
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{
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gd->used_laws &= ~(1 << idx);
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out_be32(LAWAR_ADDR(idx), 0);
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set_law_base_addr(idx, 0);
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/* Read back so that we sync the writes */
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in_be32(LAWAR_ADDR(idx));
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return;
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}
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#ifndef CONFIG_NAND_SPL
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static int get_law_entry(u8 i, struct law_entry *e)
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{
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u32 lawar;
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lawar = in_be32(LAWAR_ADDR(i));
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if (!(lawar & LAW_EN))
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return 0;
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e->addr = get_law_base_addr(i);
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e->size = lawar & 0x3f;
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e->trgt_id = (lawar >> 20) & 0xff;
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return 1;
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}
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#endif
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int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
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{
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u32 idx = ffz(gd->used_laws);
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if (idx >= FSL_HW_NUM_LAWS)
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return -1;
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set_law(idx, addr, sz, id);
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return idx;
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}
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#ifndef CONFIG_NAND_SPL
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int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
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{
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u32 idx;
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/* we have no LAWs free */
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if (gd->used_laws == -1)
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return -1;
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/* grab the last free law */
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idx = __ilog2(~(gd->used_laws));
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if (idx >= FSL_HW_NUM_LAWS)
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return -1;
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set_law(idx, addr, sz, id);
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return idx;
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}
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struct law_entry find_law(phys_addr_t addr)
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{
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struct law_entry entry;
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int i;
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entry.index = -1;
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entry.addr = 0;
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entry.size = 0;
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entry.trgt_id = 0;
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for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
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u64 upper;
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if (!get_law_entry(i, &entry))
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continue;
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upper = entry.addr + (2ull << entry.size);
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if ((addr >= entry.addr) && (addr < upper)) {
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entry.index = i;
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break;
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}
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}
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return entry;
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}
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void print_laws(void)
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{
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int i;
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u32 lawar;
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printf("\nLocal Access Window Configuration\n");
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for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
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lawar = in_be32(LAWAR_ADDR(i));
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#ifdef CONFIG_FSL_CORENET
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printf("LAWBARH%02d: 0x%08x LAWBARL%02d: 0x%08x",
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i, in_be32(LAWBARH_ADDR(i)),
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i, in_be32(LAWBARL_ADDR(i)));
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#else
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printf("LAWBAR%02d: 0x%08x", i, in_be32(LAWBAR_ADDR(i)));
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#endif
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printf(" LAWAR%02d: 0x%08x\n", i, lawar);
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printf("\t(EN: %d TGT: 0x%02x SIZE: ",
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(lawar & LAW_EN) ? 1 : 0, (lawar >> 20) & 0xff);
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print_size(lawar_size(lawar), ")\n");
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}
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return;
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}
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/* use up to 2 LAWs for DDR, used the last available LAWs */
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int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
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{
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u64 start_align, law_sz;
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int law_sz_enc;
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if (start == 0)
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start_align = 1ull << (LAW_SIZE_32G + 1);
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else
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start_align = 1ull << (ffs64(start) - 1);
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law_sz = min(start_align, sz);
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law_sz_enc = __ilog2_u64(law_sz) - 1;
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if (set_last_law(start, law_sz_enc, id) < 0)
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return -1;
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/* recalculate size based on what was actually covered by the law */
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law_sz = 1ull << __ilog2_u64(law_sz);
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/* do we still have anything to map */
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sz = sz - law_sz;
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if (sz) {
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start += law_sz;
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start_align = 1ull << (ffs64(start) - 1);
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law_sz = min(start_align, sz);
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law_sz_enc = __ilog2_u64(law_sz) - 1;
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if (set_last_law(start, law_sz_enc, id) < 0)
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return -1;
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} else {
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return 0;
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}
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/* do we still have anything to map */
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sz = sz - law_sz;
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if (sz)
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return 1;
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return 0;
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}
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#endif
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void init_laws(void)
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{
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int i;
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#if FSL_HW_NUM_LAWS < 32
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gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1);
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#elif FSL_HW_NUM_LAWS == 32
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gd->used_laws = 0;
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#else
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#error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
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#endif
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/*
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* Any LAWs that were set up before we booted assume they are meant to
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* be around and mark them used.
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*/
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for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
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u32 lawar = in_be32(LAWAR_ADDR(i));
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if (lawar & LAW_EN)
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gd->used_laws |= (1 << i);
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}
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#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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/*
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* in NAND boot we've already parsed the law_table and setup those LAWs
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* so don't do it again.
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*/
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return;
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#endif
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for (i = 0; i < num_law_entries; i++) {
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if (law_table[i].index == -1)
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set_next_law(law_table[i].addr, law_table[i].size,
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law_table[i].trgt_id);
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else
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set_law(law_table[i].index, law_table[i].addr,
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law_table[i].size, law_table[i].trgt_id);
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}
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#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
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/* check RCW to get which port is used for boot */
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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u32 bootloc = in_be32(&gur->rcwsr[6]);
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/*
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* in SRIO or PCIE boot we need to set specail LAWs for
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* SRIO or PCIE interfaces.
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*/
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switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) {
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case 0x0: /* boot from PCIE1 */
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set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
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LAW_SIZE_1M,
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LAW_TRGT_IF_PCIE_1);
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set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
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LAW_SIZE_1M,
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LAW_TRGT_IF_PCIE_1);
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break;
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case 0x1: /* boot from PCIE2 */
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set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
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LAW_SIZE_1M,
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LAW_TRGT_IF_PCIE_2);
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set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
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LAW_SIZE_1M,
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LAW_TRGT_IF_PCIE_2);
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break;
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case 0x2: /* boot from PCIE3 */
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set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
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LAW_SIZE_1M,
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LAW_TRGT_IF_PCIE_3);
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set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
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LAW_SIZE_1M,
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LAW_TRGT_IF_PCIE_3);
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break;
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case 0x8: /* boot from SRIO1 */
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set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
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LAW_SIZE_1M,
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LAW_TRGT_IF_RIO_1);
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set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
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LAW_SIZE_1M,
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LAW_TRGT_IF_RIO_1);
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break;
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case 0x9: /* boot from SRIO2 */
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set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
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LAW_SIZE_1M,
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LAW_TRGT_IF_RIO_2);
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set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
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LAW_SIZE_1M,
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LAW_TRGT_IF_RIO_2);
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break;
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default:
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break;
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}
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#endif
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return ;
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}
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