mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-17 07:28:51 +09:00
![Dirk Eibach](/assets/img/avatar_default.png)
Add a new iocon flavor with a second communiction port per channel. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
708 lines
13 KiB
C
708 lines
13 KiB
C
/*
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* (C) Copyright 2010
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <errno.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/ppc4xx-gpio.h>
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#include "405ep.h"
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#include <gdsys_fpga.h>
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#include "../common/osd.h"
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#include "../common/mclink.h"
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#include <i2c.h>
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#include <pca953x.h>
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#include <pca9698.h>
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#include <miiphy.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
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#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
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#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
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#define MAX_MUX_CHANNELS 2
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enum {
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UNITTYPE_MAIN_SERVER = 0,
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UNITTYPE_MAIN_USER = 1,
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UNITTYPE_VIDEO_SERVER = 2,
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UNITTYPE_VIDEO_USER = 3,
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};
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enum {
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HWVER_100 = 0,
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HWVER_104 = 1,
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HWVER_110 = 2,
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HWVER_120 = 3,
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HWVER_200 = 4,
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HWVER_210 = 5,
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HWVER_220 = 6,
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HWVER_230 = 7,
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};
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enum {
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FPGA_HWVER_200 = 0,
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FPGA_HWVER_210 = 1,
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};
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enum {
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COMPRESSION_NONE = 0,
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COMPRESSION_TYPE1_DELTA = 1,
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COMPRESSION_TYPE1_TYPE2_DELTA = 3,
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};
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enum {
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AUDIO_NONE = 0,
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AUDIO_TX = 1,
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AUDIO_RX = 2,
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AUDIO_RXTX = 3,
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};
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enum {
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SYSCLK_147456 = 0,
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};
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enum {
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RAM_DDR2_32 = 0,
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RAM_DDR3_32 = 1,
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};
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enum {
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CARRIER_SPEED_1G = 0,
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CARRIER_SPEED_2_5G = 1,
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};
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enum {
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MCFPGA_DONE = 1 << 0,
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MCFPGA_INIT_N = 1 << 1,
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MCFPGA_PROGRAM_N = 1 << 2,
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MCFPGA_UPDATE_ENABLE_N = 1 << 3,
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MCFPGA_RESET_N = 1 << 4,
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};
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enum {
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GPIO_MDC = 1 << 14,
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GPIO_MDIO = 1 << 15,
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};
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unsigned int mclink_fpgacount;
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struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
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static int setup_88e1518(const char *bus, unsigned char addr);
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static int verify_88e1518(const char *bus, unsigned char addr);
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int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
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{
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int res;
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switch (fpga) {
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case 0:
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out_le16(reg, data);
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break;
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default:
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res = mclink_send(fpga - 1, regoff, data);
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if (res < 0) {
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printf("mclink_send reg %02lx data %04x returned %d\n",
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regoff, data, res);
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return res;
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}
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break;
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}
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return 0;
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}
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int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
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{
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int res;
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switch (fpga) {
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case 0:
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*data = in_le16(reg);
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break;
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default:
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if (fpga > mclink_fpgacount)
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return -EINVAL;
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res = mclink_receive(fpga - 1, regoff, data);
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if (res < 0) {
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printf("mclink_receive reg %02lx returned %d\n",
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regoff, res);
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return res;
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}
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}
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return 0;
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}
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/*
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* Check Board Identity:
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*/
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int checkboard(void)
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{
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char *s = getenv("serial#");
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puts("Board: ");
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puts("IoCon");
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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puts("\n");
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return 0;
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}
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static void print_fpga_info(unsigned int fpga, bool rgmii2_present)
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{
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u16 versions;
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u16 fpga_version;
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u16 fpga_features;
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unsigned unit_type;
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unsigned hardware_version;
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unsigned feature_compression;
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unsigned feature_osd;
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unsigned feature_audio;
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unsigned feature_sysclock;
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unsigned feature_ramconfig;
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unsigned feature_carrier_speed;
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unsigned feature_carriers;
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unsigned feature_video_channels;
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int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
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FPGA_GET_REG(0, versions, &versions);
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FPGA_GET_REG(0, fpga_version, &fpga_version);
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FPGA_GET_REG(0, fpga_features, &fpga_features);
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unit_type = (versions & 0xf000) >> 12;
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feature_compression = (fpga_features & 0xe000) >> 13;
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feature_osd = fpga_features & (1<<11);
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feature_audio = (fpga_features & 0x0600) >> 9;
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feature_sysclock = (fpga_features & 0x0180) >> 7;
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feature_ramconfig = (fpga_features & 0x0060) >> 5;
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feature_carrier_speed = fpga_features & (1<<4);
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feature_carriers = (fpga_features & 0x000c) >> 2;
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feature_video_channels = fpga_features & 0x0003;
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if (legacy)
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printf("legacy ");
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switch (unit_type) {
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case UNITTYPE_MAIN_USER:
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printf("Mainchannel");
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break;
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case UNITTYPE_VIDEO_USER:
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printf("Videochannel");
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break;
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default:
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printf("UnitType %d(not supported)", unit_type);
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break;
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}
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if (unit_type == UNITTYPE_MAIN_USER) {
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if (legacy)
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hardware_version =
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(in_le16((void *)LATCH2_BASE)>>8) & 0x0f;
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else
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hardware_version =
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(!!pca9698_get_value(0x20, 24) << 0)
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| (!!pca9698_get_value(0x20, 25) << 1)
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| (!!pca9698_get_value(0x20, 26) << 2)
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| (!!pca9698_get_value(0x20, 27) << 3);
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switch (hardware_version) {
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case HWVER_100:
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printf(" HW-Ver 1.00,");
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break;
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case HWVER_104:
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printf(" HW-Ver 1.04,");
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break;
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case HWVER_110:
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printf(" HW-Ver 1.10,");
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break;
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case HWVER_120:
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printf(" HW-Ver 1.20-1.21,");
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break;
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case HWVER_200:
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printf(" HW-Ver 2.00,");
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break;
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case HWVER_210:
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printf(" HW-Ver 2.10,");
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break;
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case HWVER_220:
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printf(" HW-Ver 2.20,");
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break;
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case HWVER_230:
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printf(" HW-Ver 2.30,");
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break;
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default:
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printf(" HW-Ver %d(not supported),",
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hardware_version);
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break;
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}
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if (rgmii2_present)
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printf(" RGMII2,");
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}
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if (unit_type == UNITTYPE_VIDEO_USER) {
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hardware_version = versions & 0x000f;
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switch (hardware_version) {
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case FPGA_HWVER_200:
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printf(" HW-Ver 2.00,");
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break;
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case FPGA_HWVER_210:
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printf(" HW-Ver 2.10,");
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break;
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default:
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printf(" HW-Ver %d(not supported),",
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hardware_version);
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break;
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}
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}
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printf(" FPGA V %d.%02d\n features:",
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fpga_version / 100, fpga_version % 100);
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switch (feature_compression) {
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case COMPRESSION_NONE:
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printf(" no compression");
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break;
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case COMPRESSION_TYPE1_DELTA:
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printf(" type1-deltacompression");
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break;
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case COMPRESSION_TYPE1_TYPE2_DELTA:
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printf(" type1-deltacompression, type2-inlinecompression");
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break;
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default:
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printf(" compression %d(not supported)", feature_compression);
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break;
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}
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printf(", %sosd", feature_osd ? "" : "no ");
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switch (feature_audio) {
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case AUDIO_NONE:
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printf(", no audio");
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break;
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case AUDIO_TX:
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printf(", audio tx");
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break;
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case AUDIO_RX:
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printf(", audio rx");
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break;
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case AUDIO_RXTX:
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printf(", audio rx+tx");
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break;
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default:
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printf(", audio %d(not supported)", feature_audio);
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break;
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}
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puts(",\n ");
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switch (feature_sysclock) {
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case SYSCLK_147456:
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printf("clock 147.456 MHz");
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break;
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default:
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printf("clock %d(not supported)", feature_sysclock);
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break;
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}
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switch (feature_ramconfig) {
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case RAM_DDR2_32:
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printf(", RAM 32 bit DDR2");
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break;
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case RAM_DDR3_32:
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printf(", RAM 32 bit DDR3");
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break;
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default:
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printf(", RAM %d(not supported)", feature_ramconfig);
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break;
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}
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printf(", %d carrier(s) %s", feature_carriers,
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feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
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printf(", %d video channel(s)\n", feature_video_channels);
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}
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int last_stage_init(void)
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{
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int slaves;
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unsigned int k;
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unsigned int mux_ch;
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unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
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int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
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u16 fpga_features;
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int feature_carrier_speed = fpga_features & (1<<4);
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bool ch0_rgmii2_present = false;
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FPGA_GET_REG(0, fpga_features, &fpga_features);
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if (!legacy)
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ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
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print_fpga_info(0, ch0_rgmii2_present);
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osd_probe(0);
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/* wait for FPGA done */
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for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
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unsigned int ctr = 0;
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if (i2c_probe(mclink_controllers[k]))
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continue;
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while (!(pca953x_get_val(mclink_controllers[k])
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& MCFPGA_DONE)) {
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udelay(100000);
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if (ctr++ > 5) {
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printf("no done for mclink_controller %d\n", k);
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break;
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}
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}
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}
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if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) {
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miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
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bb_miiphy_write);
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for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
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if ((mux_ch == 1) && !ch0_rgmii2_present)
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continue;
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if (!verify_88e1518(bb_miiphy_buses[0].name, mux_ch)) {
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printf("Fixup 88e1518 erratum on %s phy %u\n",
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bb_miiphy_buses[0].name, mux_ch);
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setup_88e1518(bb_miiphy_buses[0].name, mux_ch);
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}
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}
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}
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/* wait for slave-PLLs to be up and running */
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udelay(500000);
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mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
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slaves = mclink_probe();
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mclink_fpgacount = 0;
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if (slaves <= 0)
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return 0;
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mclink_fpgacount = slaves;
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for (k = 1; k <= slaves; ++k) {
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FPGA_GET_REG(k, fpga_features, &fpga_features);
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feature_carrier_speed = fpga_features & (1<<4);
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print_fpga_info(k, false);
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osd_probe(k);
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if (feature_carrier_speed == CARRIER_SPEED_1G) {
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miiphy_register(bb_miiphy_buses[k].name,
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bb_miiphy_read, bb_miiphy_write);
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if (!verify_88e1518(bb_miiphy_buses[k].name, 0)) {
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printf("Fixup 88e1518 erratum on %s\n",
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bb_miiphy_buses[k].name);
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setup_88e1518(bb_miiphy_buses[k].name, 0);
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}
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}
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}
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return 0;
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}
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/*
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* provide access to fpga gpios (for I2C bitbang)
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* (these may look all too simple but make iocon.h much more readable)
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*/
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void fpga_gpio_set(unsigned int bus, int pin)
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{
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FPGA_SET_REG(bus, gpio.set, pin);
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}
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void fpga_gpio_clear(unsigned int bus, int pin)
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{
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FPGA_SET_REG(bus, gpio.clear, pin);
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}
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int fpga_gpio_get(unsigned int bus, int pin)
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{
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u16 val;
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FPGA_GET_REG(bus, gpio.read, &val);
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return val & pin;
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}
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void gd405ep_init(void)
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{
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unsigned int k;
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if (i2c_probe(0x20)) { /* i2c_probe returns 0 on success */
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
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gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
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} else {
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pca9698_direction_output(0x20, 4, 1);
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}
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}
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void gd405ep_set_fpga_reset(unsigned state)
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{
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int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
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if (legacy) {
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if (state) {
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out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
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out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
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} else {
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out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
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out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
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}
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} else {
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pca9698_set_value(0x20, 4, state ? 0 : 1);
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}
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}
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void gd405ep_setup_hw(void)
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{
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/*
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* set "startup-finished"-gpios
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*/
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gpio_write_bit(21, 0);
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gpio_write_bit(22, 1);
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}
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int gd405ep_get_fpga_done(unsigned fpga)
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{
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int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
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if (legacy)
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return in_le16((void *)LATCH2_BASE)
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& CONFIG_SYS_FPGA_DONE(fpga);
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else
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return pca9698_get_value(0x20, 20);
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}
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/*
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* FPGA MII bitbang implementation
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*/
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struct fpga_mii {
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unsigned fpga;
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int mdio;
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} fpga_mii[] = {
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{ 0, 1},
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{ 1, 1},
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{ 2, 1},
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{ 3, 1},
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};
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static int mii_dummy_init(struct bb_miiphy_bus *bus)
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{
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return 0;
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}
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static int mii_mdio_active(struct bb_miiphy_bus *bus)
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{
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struct fpga_mii *fpga_mii = bus->priv;
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if (fpga_mii->mdio)
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FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
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else
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FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
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return 0;
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}
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static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
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{
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struct fpga_mii *fpga_mii = bus->priv;
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FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
|
|
{
|
|
struct fpga_mii *fpga_mii = bus->priv;
|
|
|
|
if (v)
|
|
FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
|
|
else
|
|
FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
|
|
|
|
fpga_mii->mdio = v;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
|
|
{
|
|
u16 gpio;
|
|
struct fpga_mii *fpga_mii = bus->priv;
|
|
|
|
FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
|
|
|
|
*v = ((gpio & GPIO_MDIO) != 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
|
|
{
|
|
struct fpga_mii *fpga_mii = bus->priv;
|
|
|
|
if (v)
|
|
FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
|
|
else
|
|
FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mii_delay(struct bb_miiphy_bus *bus)
|
|
{
|
|
udelay(1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct bb_miiphy_bus bb_miiphy_buses[] = {
|
|
{
|
|
.name = "board0",
|
|
.init = mii_dummy_init,
|
|
.mdio_active = mii_mdio_active,
|
|
.mdio_tristate = mii_mdio_tristate,
|
|
.set_mdio = mii_set_mdio,
|
|
.get_mdio = mii_get_mdio,
|
|
.set_mdc = mii_set_mdc,
|
|
.delay = mii_delay,
|
|
.priv = &fpga_mii[0],
|
|
},
|
|
{
|
|
.name = "board1",
|
|
.init = mii_dummy_init,
|
|
.mdio_active = mii_mdio_active,
|
|
.mdio_tristate = mii_mdio_tristate,
|
|
.set_mdio = mii_set_mdio,
|
|
.get_mdio = mii_get_mdio,
|
|
.set_mdc = mii_set_mdc,
|
|
.delay = mii_delay,
|
|
.priv = &fpga_mii[1],
|
|
},
|
|
{
|
|
.name = "board2",
|
|
.init = mii_dummy_init,
|
|
.mdio_active = mii_mdio_active,
|
|
.mdio_tristate = mii_mdio_tristate,
|
|
.set_mdio = mii_set_mdio,
|
|
.get_mdio = mii_get_mdio,
|
|
.set_mdc = mii_set_mdc,
|
|
.delay = mii_delay,
|
|
.priv = &fpga_mii[2],
|
|
},
|
|
{
|
|
.name = "board3",
|
|
.init = mii_dummy_init,
|
|
.mdio_active = mii_mdio_active,
|
|
.mdio_tristate = mii_mdio_tristate,
|
|
.set_mdio = mii_set_mdio,
|
|
.get_mdio = mii_get_mdio,
|
|
.set_mdc = mii_set_mdc,
|
|
.delay = mii_delay,
|
|
.priv = &fpga_mii[3],
|
|
},
|
|
};
|
|
|
|
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
|
|
sizeof(bb_miiphy_buses[0]);
|
|
|
|
/*
|
|
* Workaround for erratum mentioned in 88E1518 release notes
|
|
*/
|
|
|
|
static int verify_88e1518(const char *bus, unsigned char addr)
|
|
{
|
|
u16 phy_id1, phy_id2;
|
|
|
|
if (miiphy_read(bus, addr, 2, &phy_id1) ||
|
|
miiphy_read(bus, addr, 3, &phy_id2)) {
|
|
printf("Error reading from the PHY addr=%02x\n", addr);
|
|
return -EIO;
|
|
}
|
|
|
|
if ((phy_id1 != 0x0141) || ((phy_id2 & 0xfff0) != 0x0dd0))
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct regfix_88e1518 {
|
|
u8 reg;
|
|
u16 data;
|
|
} regfix_88e1518[] = {
|
|
{ 22, 0x00ff },
|
|
{ 17, 0x214b },
|
|
{ 16, 0x2144 },
|
|
{ 17, 0x0c28 },
|
|
{ 16, 0x2146 },
|
|
{ 17, 0xb233 },
|
|
{ 16, 0x214d },
|
|
{ 17, 0xcc0c },
|
|
{ 16, 0x2159 },
|
|
{ 22, 0x00fb },
|
|
{ 7, 0xc00d },
|
|
{ 22, 0x0000 },
|
|
};
|
|
|
|
static int setup_88e1518(const char *bus, unsigned char addr)
|
|
{
|
|
unsigned int k;
|
|
|
|
for (k = 0; k < ARRAY_SIZE(regfix_88e1518); ++k) {
|
|
if (miiphy_write(bus, addr,
|
|
regfix_88e1518[k].reg,
|
|
regfix_88e1518[k].data)) {
|
|
printf("Error writing to the PHY addr=%02x\n", addr);
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|