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https://github.com/brain-hackers/u-boot-brain
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d755a5fb20
The hardware DQS gate training is a bit unreliable and does not always find the best delay settings. So we introduce a 32-bit 'dqs_gating_delay' variable, where each byte encodes the DQS gating delay for each byte lane. The delay granularity is 1/4 cycle. Also we allow to enable the active DQS gating window mode, which works better than the passive mode in practice. The DDR3 spec says that there is a 0.9 cycles preamble and 0.3 cycle postamble. The DQS window has to be opened during preamble and closed during postamble. In the passive window mode, the gating window is opened and closed by just using the gating delay settings. And because of the 1/4 cycle delay granularity, accurately hitting the 0.3 cycle long postamble is a bit tough. In the active window mode, the gating window is auto-closing with the help of monitoring the DQS line, which relaxes the gating delay accuracy requirements. But the hardware DQS gate training is still performed in the passive window mode. It is a more strict test, which is reducing the results variance compared to the training with active window mode. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
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| am33xx | ||
| at91 | ||
| bcm281xx | ||
| exynos | ||
| highbank | ||
| keystone | ||
| kona-common | ||
| mx5 | ||
| mx6 | ||
| omap3 | ||
| omap4 | ||
| omap5 | ||
| omap-common | ||
| rmobile | ||
| s5p-common | ||
| s5pc1xx | ||
| socfpga | ||
| sunxi | ||
| tegra20 | ||
| tegra30 | ||
| tegra114 | ||
| tegra124 | ||
| tegra-common | ||
| u8500 | ||
| vf610 | ||
| zynq | ||
| arch_timer.c | ||
| cache_v7.c | ||
| config.mk | ||
| cpu.c | ||
| lowlevel_init.S | ||
| Makefile | ||
| nonsec_virt.S | ||
| psci.S | ||
| start.S | ||
| syslib.c | ||
| virt-dt.c | ||
| virt-v7.c | ||