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https://github.com/brain-hackers/u-boot-brain
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![Chander Kashyap](/assets/img/avatar_default.png)
As per new naming convention for Samsung SoC's, all Cortex-A9 and Cortex-A15 based SoC's will be classified under the name Exynos. Cortex-A9 and Cortex-A15 based SoC's will be sub-classified as Exynos4 and Exynos5 respectively. In order to better adapt and reuse code across various upcoming Samsung Exynos based boards, all uses of s5pc210 prefix/suffix/directory-names are renamed in this patch. s5pc210 is renamed as exynos4210 and S5PC210/s5pc210 suffix/prefix are renamed as exynos4/EXYNOS4. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
422 lines
8.7 KiB
ArmAsm
422 lines
8.7 KiB
ArmAsm
/*
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* Memory setup for ORIGEN board based on EXYNOS4210
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*
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* Copyright (C) 2011 Samsung Electronics
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include "origen_setup.h"
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#define SET_MIU
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.globl mem_ctrl_asm_init
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mem_ctrl_asm_init:
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/*
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* Async bridge configuration at CPU_core:
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* 1: half_sync
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* 0: full_sync
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*/
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ldr r0, =ASYNC_CONFIG
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mov r1, #1
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str r1, [r0]
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#ifdef SET_MIU
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ldr r0, =EXYNOS4_MIU_BASE
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/* Interleave: 2Bit, Interleave_bit1: 0x21, Interleave_bit2: 0x7 */
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ldr r1, =0x20001507
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str r1, [r0, #APB_SFR_INTERLEAVE_CONF_OFFSET]
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/* Update MIU Configuration */
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ldr r1, =0x00000001
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str r1, [r0, #APB_SFR_ARBRITATION_CONF_OFFSET]
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#endif
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/* DREX0 */
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ldr r0, =EXYNOS4_DMC0_BASE
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/*
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* DLL Parameter Setting:
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* Termination: Enable R/W
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* Phase Delay for DQS Cleaning: 180' Shift
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*/
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ldr r1, =0xe0000086
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str r1, [r0, #DMC_PHYCONTROL1]
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/*
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* ZQ Calibration
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* Termination: Disable
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* Auto Calibration Start: Enable
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*/
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ldr r1, =0xE3855703
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str r1, [r0, #DMC_PHYZQCONTROL]
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/* Wait ?us*/
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mov r2, #0x100000
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1: subs r2, r2, #1
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bne 1b
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/*
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* Update DLL Information:
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* Force DLL Resyncronization
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*/
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ldr r1, =0xe000008e
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str r1, [r0, #DMC_PHYCONTROL1]
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/* Reset Force DLL Resyncronization */
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ldr r1, =0xe0000086
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str r1, [r0, #DMC_PHYCONTROL1]
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/* Enable Differential DQS, DLL Off*/
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ldr r1, =0x71101008
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str r1, [r0, #DMC_PHYCONTROL0]
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/* Activate PHY DLL: DLL On */
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ldr r1, =0x7110100A
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str r1, [r0, #DMC_PHYCONTROL0]
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/* Set DLL Parameters */
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ldr r1, =0xe0000086
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str r1, [r0, #DMC_PHYCONTROL1]
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/* DLL Start */
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ldr r1, =0x7110100B
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str r1, [r0, #DMC_PHYCONTROL0]
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ldr r1, =0x00000000
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str r1, [r0, #DMC_PHYCONTROL2]
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/* Set Clock Ratio of Bus clock to Memory Clock */
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ldr r1, =0x0FFF301a
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str r1, [r0, #DMC_CONCONTROL]
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/*
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* Memor Burst length: 8
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* Number of chips: 2
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* Memory Bus width: 32 bit
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* Memory Type: DDR3
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* Additional Latancy for PLL: 1 Cycle
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*/
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ldr r1, =0x00312640
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str r1, [r0, #DMC_MEMCONTROL]
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/*
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* Memory Configuration Chip 0
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* Address Mapping: Interleaved
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* Number of Column address Bits: 10 bits
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* Number of Rows Address Bits: 14
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* Number of Banks: 8
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*/
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ldr r1, =0x20e01323
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str r1, [r0, #DMC_MEMCONFIG0]
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/*
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* Memory Configuration Chip 1
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* Address Mapping: Interleaved
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* Number of Column address Bits: 10 bits
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* Number of Rows Address Bits: 14
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* Number of Banks: 8
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*/
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ldr r1, =0x40e01323
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str r1, [r0, #DMC_MEMCONFIG1]
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/* Config Precharge Policy */
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ldr r1, =0xff000000
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str r1, [r0, #DMC_PRECHCONFIG]
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/*
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* TimingAref, TimingRow, TimingData, TimingPower Setting:
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* Values as per Memory AC Parameters
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*/
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ldr r1, =0x000000BB
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str r1, [r0, #DMC_TIMINGAREF]
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ldr r1, =0x4046654f
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str r1, [r0, #DMC_TIMINGROW]
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ldr r1, =0x46400506
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str r1, [r0, #DMC_TIMINGDATA]
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ldr r1, =0x52000A3C
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str r1, [r0, #DMC_TIMINGPOWER]
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/* Chip0: NOP Command: Assert and Hold CKE to high level */
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ldr r1, =0x07000000
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str r1, [r0, #DMC_DIRECTCMD]
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/* Wait ?us*/
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mov r2, #0x100000
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2: subs r2, r2, #1
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bne 2b
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/* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
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ldr r1, =0x00020000
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str r1, [r0, #DMC_DIRECTCMD]
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ldr r1, =0x00030000
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str r1, [r0, #DMC_DIRECTCMD]
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ldr r1, =0x00010002
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str r1, [r0, #DMC_DIRECTCMD]
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ldr r1, =0x00000328
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str r1, [r0, #DMC_DIRECTCMD]
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/* Wait ?us*/
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mov r2, #0x100000
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3: subs r2, r2, #1
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bne 3b
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/* Chip0: ZQINIT */
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ldr r1, =0x0a000000
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str r1, [r0, #DMC_DIRECTCMD]
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/* Wait ?us*/
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mov r2, #0x100000
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4: subs r2, r2, #1
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bne 4b
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/* Chip1: NOP Command: Assert and Hold CKE to high level */
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ldr r1, =0x07100000
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str r1, [r0, #DMC_DIRECTCMD]
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/* Wait ?us*/
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mov r2, #0x100000
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5: subs r2, r2, #1
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bne 5b
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/* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
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ldr r1, =0x00120000
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str r1, [r0, #DMC_DIRECTCMD]
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ldr r1, =0x00130000
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str r1, [r0, #DMC_DIRECTCMD]
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ldr r1, =0x00110002
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str r1, [r0, #DMC_DIRECTCMD]
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ldr r1, =0x00100328
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str r1, [r0, #DMC_DIRECTCMD]
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/* Wait ?us*/
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mov r2, #0x100000
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6: subs r2, r2, #1
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bne 6b
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/* Chip1: ZQINIT */
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ldr r1, =0x0a100000
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str r1, [r0, #DMC_DIRECTCMD]
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/* Wait ?us*/
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mov r2, #0x100000
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7: subs r2, r2, #1
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bne 7b
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ldr r1, =0xe000008e
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str r1, [r0, #DMC_PHYCONTROL1]
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ldr r1, =0xe0000086
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str r1, [r0, #DMC_PHYCONTROL1]
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/* Wait ?us*/
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mov r2, #0x100000
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8: subs r2, r2, #1
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bne 8b
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/* DREX1 */
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ldr r0, =EXYNOS4_DMC1_BASE @0x10410000
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/*
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* DLL Parameter Setting:
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* Termination: Enable R/W
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* Phase Delay for DQS Cleaning: 180' Shift
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*/
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ldr r1, =0xe0000086
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str r1, [r0, #DMC_PHYCONTROL1]
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/*
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* ZQ Calibration:
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* Termination: Disable
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* Auto Calibration Start: Enable
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*/
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ldr r1, =0xE3855703
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str r1, [r0, #DMC_PHYZQCONTROL]
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/* Wait ?us*/
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mov r2, #0x100000
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1: subs r2, r2, #1
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bne 1b
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/*
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* Update DLL Information:
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* Force DLL Resyncronization
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*/
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ldr r1, =0xe000008e
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str r1, [r0, #DMC_PHYCONTROL1]
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/* Reset Force DLL Resyncronization */
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ldr r1, =0xe0000086
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str r1, [r0, #DMC_PHYCONTROL1]
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/* Enable Differential DQS, DLL Off*/
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ldr r1, =0x71101008
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str r1, [r0, #DMC_PHYCONTROL0]
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/* Activate PHY DLL: DLL On */
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ldr r1, =0x7110100A
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str r1, [r0, #DMC_PHYCONTROL0]
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/* Set DLL Parameters */
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ldr r1, =0xe0000086
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str r1, [r0, #DMC_PHYCONTROL1]
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/* DLL Start */
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ldr r1, =0x7110100B
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str r1, [r0, #DMC_PHYCONTROL0]
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ldr r1, =0x00000000
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str r1, [r0, #DMC_PHYCONTROL2]
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/* Set Clock Ratio of Bus clock to Memory Clock */
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ldr r1, =0x0FFF301a
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str r1, [r0, #DMC_CONCONTROL]
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/*
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* Memor Burst length: 8
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* Number of chips: 2
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* Memory Bus width: 32 bit
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* Memory Type: DDR3
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* Additional Latancy for PLL: 1 Cycle
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*/
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ldr r1, =0x00312640
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str r1, [r0, #DMC_MEMCONTROL]
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/*
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* Memory Configuration Chip 0
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* Address Mapping: Interleaved
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* Number of Column address Bits: 10 bits
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* Number of Rows Address Bits: 14
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* Number of Banks: 8
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*/
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ldr r1, =0x20e01323
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str r1, [r0, #DMC_MEMCONFIG0]
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/*
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* Memory Configuration Chip 1
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* Address Mapping: Interleaved
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* Number of Column address Bits: 10 bits
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* Number of Rows Address Bits: 14
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* Number of Banks: 8
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*/
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ldr r1, =0x40e01323
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str r1, [r0, #DMC_MEMCONFIG1]
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/* Config Precharge Policy */
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ldr r1, =0xff000000
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str r1, [r0, #DMC_PRECHCONFIG]
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/*
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* TimingAref, TimingRow, TimingData, TimingPower Setting:
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* Values as per Memory AC Parameters
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*/
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ldr r1, =0x000000BB
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str r1, [r0, #DMC_TIMINGAREF]
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ldr r1, =0x4046654f
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str r1, [r0, #DMC_TIMINGROW]
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ldr r1, =0x46400506
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str r1, [r0, #DMC_TIMINGDATA]
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ldr r1, =0x52000A3C
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str r1, [r0, #DMC_TIMINGPOWER]
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/* Chip0: NOP Command: Assert and Hold CKE to high level */
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ldr r1, =0x07000000
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str r1, [r0, #DMC_DIRECTCMD]
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/* Wait ?us*/
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mov r2, #0x100000
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2: subs r2, r2, #1
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bne 2b
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/* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
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ldr r1, =0x00020000
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str r1, [r0, #DMC_DIRECTCMD]
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ldr r1, =0x00030000
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str r1, [r0, #DMC_DIRECTCMD]
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ldr r1, =0x00010002
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str r1, [r0, #DMC_DIRECTCMD]
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ldr r1, =0x00000328
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str r1, [r0, #DMC_DIRECTCMD]
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/* Wait ?us*/
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mov r2, #0x100000
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3: subs r2, r2, #1
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bne 3b
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/* Chip 0: ZQINIT */
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ldr r1, =0x0a000000
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str r1, [r0, #DMC_DIRECTCMD]
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/* Wait ?us*/
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mov r2, #0x100000
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4: subs r2, r2, #1
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bne 4b
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/* Chip1: NOP Command: Assert and Hold CKE to high level */
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ldr r1, =0x07100000
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str r1, [r0, #DMC_DIRECTCMD]
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/* Wait ?us*/
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mov r2, #0x100000
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5: subs r2, r2, #1
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bne 5b
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/* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
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ldr r1, =0x00120000
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str r1, [r0, #DMC_DIRECTCMD]
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ldr r1, =0x00130000
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str r1, [r0, #DMC_DIRECTCMD]
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ldr r1, =0x00110002
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str r1, [r0, #DMC_DIRECTCMD]
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ldr r1, =0x00100328
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str r1, [r0, #DMC_DIRECTCMD]
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/* Wait ?us*/
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mov r2, #0x100000
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6: subs r2, r2, #1
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bne 6b
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/* Chip1: ZQINIT */
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ldr r1, =0x0a100000
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str r1, [r0, #DMC_DIRECTCMD]
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/* Wait ?us*/
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mov r2, #0x100000
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7: subs r2, r2, #1
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bne 7b
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ldr r1, =0xe000008e
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str r1, [r0, #DMC_PHYCONTROL1]
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ldr r1, =0xe0000086
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str r1, [r0, #DMC_PHYCONTROL1]
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/* Wait ?us*/
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mov r2, #0x100000
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8: subs r2, r2, #1
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bne 8b
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/* turn on DREX0, DREX1 */
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ldr r0, =EXYNOS4_DMC0_BASE
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ldr r1, =0x0FFF303a
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str r1, [r0, #DMC_CONCONTROL]
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ldr r0, =EXYNOS4_DMC1_BASE
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ldr r1, =0x0FFF303a
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str r1, [r0, #DMC_CONCONTROL]
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mov pc, lr
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