mirror of
https://github.com/brain-hackers/u-boot-brain
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![Marek Vasut](/assets/img/avatar_default.png)
Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de>
217 lines
4.9 KiB
C
217 lines
4.9 KiB
C
/*
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* DENX M28 module
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux-mx28.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/mii.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <errno.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Functions
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*/
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int board_early_init_f(void)
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{
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/* IO0 clock at 480MHz */
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mx28_set_ioclk(MXC_IOCLK0, 480000);
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/* IO1 clock at 480MHz */
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mx28_set_ioclk(MXC_IOCLK1, 480000);
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/* SSP0 clock at 96MHz */
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mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
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/* SSP2 clock at 96MHz */
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mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
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#ifdef CONFIG_CMD_USB
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mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
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mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 |
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MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
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gpio_direction_output(MX28_PAD_AUART3_TX__GPIO_3_13, 0);
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#endif
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return 0;
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}
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int board_init(void)
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{
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/* Adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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#define HW_DIGCTRL_SCRATCH0 0x8001c280
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#define HW_DIGCTRL_SCRATCH1 0x8001c290
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int dram_init(void)
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{
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uint32_t sz[2];
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sz[0] = readl(HW_DIGCTRL_SCRATCH0);
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sz[1] = readl(HW_DIGCTRL_SCRATCH1);
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if (sz[0] != sz[1]) {
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printf("MX28:\n"
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"Error, the RAM size in HW_DIGCTRL_SCRATCH0 and\n"
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"HW_DIGCTRL_SCRATCH1 is not the same. Please\n"
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"verify these two registers contain valid RAM size!\n");
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hang();
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}
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gd->ram_size = sz[0];
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return 0;
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}
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#ifdef CONFIG_CMD_MMC
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static int m28_mmc_wp(int id)
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{
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if (id != 0) {
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printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
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return 1;
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}
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return gpio_get_value(MX28_PAD_AUART2_CTS__GPIO_3_10);
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}
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int board_mmc_init(bd_t *bis)
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{
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/* Configure WP as input. */
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gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10);
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return mxsmmc_initialize(bis, 0, m28_mmc_wp);
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}
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#endif
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#ifdef CONFIG_CMD_NET
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#define MII_OPMODE_STRAP_OVERRIDE 0x16
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#define MII_PHY_CTRL1 0x1e
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#define MII_PHY_CTRL2 0x1f
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int fecmxc_mii_postcall(int phy)
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{
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miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
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miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
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if (phy == 3)
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miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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struct mx28_clkctrl_regs *clkctrl_regs =
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(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
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struct eth_device *dev;
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int ret;
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ret = cpu_eth_init(bis);
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clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
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CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
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CLKCTRL_ENET_TIME_SEL_RMII_CLK);
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ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
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if (ret) {
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printf("FEC MXS: Unable to init FEC0\n");
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return ret;
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}
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ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
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if (ret) {
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printf("FEC MXS: Unable to init FEC1\n");
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return ret;
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}
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dev = eth_get_dev_by_name("FEC0");
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if (!dev) {
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printf("FEC MXS: Unable to get FEC0 device entry\n");
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return -EINVAL;
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}
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ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
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if (ret) {
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printf("FEC MXS: Unable to register FEC0 mii postcall\n");
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return ret;
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}
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dev = eth_get_dev_by_name("FEC1");
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if (!dev) {
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printf("FEC MXS: Unable to get FEC1 device entry\n");
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return -EINVAL;
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}
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ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
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if (ret) {
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printf("FEC MXS: Unable to register FEC1 mii postcall\n");
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return ret;
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}
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return ret;
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}
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#ifdef CONFIG_M28_FEC_MAC_IN_OCOTP
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#define MXS_OCOTP_MAX_TIMEOUT 1000000
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void imx_get_mac_from_fuse(char *mac)
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{
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struct mx28_ocotp_regs *ocotp_regs =
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(struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
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uint32_t data;
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memset(mac, 0, 6);
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writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
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if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
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MXS_OCOTP_MAX_TIMEOUT)) {
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printf("MXS FEC: Can't get MAC from OCOTP\n");
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return;
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}
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data = readl(&ocotp_regs->hw_ocotp_cust0);
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mac[0] = 0x00;
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mac[1] = 0x04;
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mac[2] = (data >> 24) & 0xff;
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mac[3] = (data >> 16) & 0xff;
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mac[4] = (data >> 8) & 0xff;
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mac[5] = data & 0xff;
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}
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#else
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void imx_get_mac_from_fuse(char *mac)
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{
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memset(mac, 0, 6);
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}
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#endif
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#endif
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