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https://github.com/brain-hackers/u-boot-brain
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![Kumar Gala](/assets/img/avatar_default.png)
While we had ft_pci_board_setup it wasn't being called by ft_board_setup. Fix that so we actually update the device tree PCI nodes on P1_P2_RDB boards. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
227 lines
5.5 KiB
C
227 lines
5.5 KiB
C
/*
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* Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <tsec.h>
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#include <vsc7385.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define VSC7385_RST_SET 0x00080000
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#define SLIC_RST_SET 0x00040000
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#define SGMII_PHY_RST_SET 0x00020000
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#define PCIE_RST_SET 0x00010000
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#define RGMII_PHY_RST_SET 0x02000000
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#define USB_RST_CLR 0x04000000
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#define GPIO_DIR 0x060f0000
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#define BOARD_PERI_RST_SET VSC7385_RST_SET | SLIC_RST_SET | \
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SGMII_PHY_RST_SET | PCIE_RST_SET | \
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RGMII_PHY_RST_SET
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#define SYSCLK_MASK 0x00200000
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#define BOARDREV_MASK 0x10100000
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#define BOARDREV_B 0x10100000
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#define BOARDREV_C 0x00100000
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#define SYSCLK_66 66666666
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#define SYSCLK_50 50000000
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#define SYSCLK_100 100000000
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unsigned long get_board_sys_clk(ulong dummy)
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{
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volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
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u32 val_gpdat, sysclk_gpio, board_rev_gpio;
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val_gpdat = pgpio->gpdat;
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sysclk_gpio = val_gpdat & SYSCLK_MASK;
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board_rev_gpio = val_gpdat & BOARDREV_MASK;
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if (board_rev_gpio == BOARDREV_C) {
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if(sysclk_gpio == 0)
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return SYSCLK_66;
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else
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return SYSCLK_100;
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} else if (board_rev_gpio == BOARDREV_B) {
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if(sysclk_gpio == 0)
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return SYSCLK_66;
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else
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return SYSCLK_50;
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}
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return 0;
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}
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#ifdef CONFIG_MMC
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int board_early_init_f (void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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setbits_be32(&gur->pmuxcr,
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(MPC85xx_PMUXCR_SDHC_CD |
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MPC85xx_PMUXCR_SDHC_WP));
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return 0;
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}
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#endif
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int checkboard (void)
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{
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u32 val_gpdat, board_rev_gpio;
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volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
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char board_rev = 0;
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struct cpu_type *cpu;
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val_gpdat = pgpio->gpdat;
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board_rev_gpio = val_gpdat & BOARDREV_MASK;
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if (board_rev_gpio == BOARDREV_C)
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board_rev = 'C';
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else if (board_rev_gpio == BOARDREV_B)
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board_rev = 'B';
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else
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panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
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cpu = gd->cpu;
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printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
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setbits_be32(&pgpio->gpdir, GPIO_DIR);
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/*
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* Bringing the following peripherals out of reset via GPIOs
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* 0 = reset and 1 = out of reset
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* GPIO12 - Reset to Ethernet Switch
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* GPIO13 - Reset to SLIC/SLAC devices
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* GPIO14 - Reset to SGMII_PHY_N
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* GPIO15 - Reset to PCIe slots
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* GPIO6 - Reset to RGMII PHY
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* GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset
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*/
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clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET);
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return 0;
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}
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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/* invalidate existing TLB entry for flash */
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disable_tlb(flash_esel);
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_16M, 1);
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return 0;
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}
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#ifdef CONFIG_TSEC_ENET
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int board_eth_init(bd_t *bis)
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{
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struct tsec_info_struct tsec_info[4];
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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int num = 0;
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char *tmp;
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unsigned int vscfw_addr;
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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num++;
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#endif
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#ifdef CONFIG_TSEC3
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SET_STD_TSEC_INFO(tsec_info[num], 3);
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
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tsec_info[num].flags |= TSEC_SGMII;
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num++;
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#endif
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if (!num) {
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printf("No TSECs initialized\n");
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return 0;
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}
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#ifdef CONFIG_VSC7385_ENET
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/* If a VSC7385 microcode image is present, then upload it. */
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if ((tmp = getenv ("vscfw_addr")) != NULL) {
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vscfw_addr = simple_strtoul (tmp, NULL, 16);
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printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
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if (vsc7385_upload_firmware((void *) vscfw_addr,
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CONFIG_VSC7385_IMAGE_SIZE))
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puts("Failure uploading VSC7385 microcode.\n");
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} else
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puts("No address specified for VSC7385 microcode.\n");
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#endif
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tsec_eth_init(bis, tsec_info, num);
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return pci_eth_init(bis);
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}
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#endif
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#if defined(CONFIG_OF_BOARD_SETUP)
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extern void ft_pci_board_setup(void *blob);
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void ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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ft_pci_board_setup(blob);
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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}
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#endif
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#ifdef CONFIG_MP
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extern void cpu_mp_lmb_reserve(struct lmb *lmb);
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void board_lmb_reserve(struct lmb *lmb)
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{
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cpu_mp_lmb_reserve(lmb);
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}
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#endif
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