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![Timur Tabi](/assets/img/avatar_default.png)
Refactor and document the Freescale PIXIS code, used on most 85xx and 86xx boards. This makes the code easier to read and more flexible. Delete pixis.h, because none of the exported functions were actually being used by any other file. Make all of the functions in pixis.c 'static'. Remove "#include pixis.h" from every file that has it. Remove some unnecessary #includes. Make 'pixis_base' into a macro, so that we don't need to define it in every function. Add "while(1);" loops at the end of functions that reset the board, so that execution doesn't continue while the reset is in progress. Replace in_8/out_8 calls with clrbits_8, setbits_8, or clrsetbits_8, where appropriate. Replace ulong/uint with their spelled-out equivalents. Remove unnecessary typecasts, changing the types of some variables if necessary. Add CONFIG_SYS_PIXIS_VCFGEN0_ENABLE and CONFIG_SYS_PIXIS_VBOOT_ENABLE to make it easier for specific boards to support variations in the PIXIS registers sets. No current boards appears to need this feature. Fix the definition of CONFIG_SYS_PIXIS_VBOOT_MASK for the MPC8610 HPCD. Apparently, "pixis_reset altbank" has never worked on this board. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
383 lines
8.5 KiB
C
383 lines
8.5 KiB
C
/*
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* Copyright 2007,2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_86xx.h>
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#include <asm/fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <spd_sdram.h>
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#include <netdev.h>
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void sdram_init(void);
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phys_size_t fixed_sdram(void);
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void mpc8610hpcd_diu_init(void);
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/* called before any console output */
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int board_early_init_f(void)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
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return 0;
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}
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int misc_init_r(void)
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{
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u8 tmp_val, version;
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u8 *pixis_base = (u8 *)PIXIS_BASE;
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/*Do not use 8259PIC*/
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tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
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out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
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/*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
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version = in_8(pixis_base + PIXIS_PVER);
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if(version >= 0x07) {
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tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
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out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
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}
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/* Using this for DIU init before the driver in linux takes over
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* Enable the TFP410 Encoder (I2C address 0x38)
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*/
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tmp_val = 0xBF;
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i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
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/* Verify if enabled */
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tmp_val = 0;
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i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
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debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
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tmp_val = 0x10;
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i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
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/* Verify if enabled */
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tmp_val = 0;
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i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
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debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
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#ifdef CONFIG_FSL_DIU_FB
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mpc8610hpcd_diu_init();
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#endif
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return 0;
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}
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int checkboard(void)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
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u8 *pixis_base = (u8 *)PIXIS_BASE;
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printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
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"System Version: 0x%02x, FPGA Version: 0x%02x\n",
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in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
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in_8(pixis_base + PIXIS_PVER));
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mcm->abcr |= 0x00010000; /* 0 */
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mcm->hpmr3 = 0x80000008; /* 4c */
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mcm->hpmr0 = 0;
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mcm->hpmr1 = 0;
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mcm->hpmr2 = 0;
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mcm->hpmr4 = 0;
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mcm->hpmr5 = 0;
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return 0;
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}
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phys_size_t
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initdram(int board_type)
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{
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phys_size_t dram_size = 0;
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#if defined(CONFIG_SPD_EEPROM)
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dram_size = fsl_ddr_sdram();
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#else
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dram_size = fixed_sdram();
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#endif
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setup_ddr_bat(dram_size);
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puts(" DDR: ");
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return dram_size;
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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phys_size_t fixed_sdram(void)
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{
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#if !defined(CONFIG_SYS_RAMBOOT)
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
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uint d_init;
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ddr->cs0_bnds = 0x0000001f;
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ddr->cs0_config = 0x80010202;
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ddr->timing_cfg_3 = 0x00000000;
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ddr->timing_cfg_0 = 0x00260802;
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ddr->timing_cfg_1 = 0x3935d322;
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ddr->timing_cfg_2 = 0x14904cc8;
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ddr->sdram_mode = 0x00480432;
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ddr->sdram_mode_2 = 0x00000000;
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ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
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ddr->sdram_data_init = 0xDEADBEEF;
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ddr->sdram_clk_cntl = 0x03800000;
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ddr->sdram_cfg_2 = 0x04400010;
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#if defined(CONFIG_DDR_ECC)
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ddr->err_int_en = 0x0000000d;
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ddr->err_disable = 0x00000000;
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ddr->err_sbe = 0x00010000;
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#endif
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asm("sync;isync");
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udelay(500);
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ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
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#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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d_init = 1;
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debug("DDR - 1st controller: memory initializing\n");
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/*
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* Poll until memory is initialized.
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* 512 Meg at 400 might hit this 200 times or so.
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*/
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while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
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udelay(1000);
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debug("DDR: memory initialized\n\n");
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asm("sync; isync");
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udelay(500);
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#endif
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return 512 * 1024 * 1024;
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#endif
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return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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}
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#endif
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#if defined(CONFIG_PCI)
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/*
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* Initialize PCI Devices, report devices found.
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*/
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_fsl86xxads_config_table[] = {
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{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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PCI_IDSEL_NUMBER, PCI_ANY_ID,
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pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
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{}
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};
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#endif
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static struct pci_controller pci1_hose = {
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#ifndef CONFIG_PCI_PNP
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config_table:pci_mpc86xxcts_config_table
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#endif
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};
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#endif /* CONFIG_PCI */
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif
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#ifdef CONFIG_PCIE2
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static struct pci_controller pcie2_hose;
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#endif
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void pci_init_board(void)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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struct fsl_pci_info pci_info[3];
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u32 devdisr, pordevsr, io_sel;
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int first_free_busno = 0;
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int num = 0;
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int pci_agent, pcie_ep, pcie_configured;
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devdisr = in_be32(&gur->devdisr);
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pordevsr = in_be32(&gur->pordevsr);
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io_sel = (pordevsr & MPC8610_PORDEVSR_IO_SEL)
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>> MPC8610_PORDEVSR_IO_SEL_SHIFT;
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debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
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#ifdef CONFIG_PCIE1
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pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
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if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){
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SET_STD_PCIE_INFO(pci_info[num], 1);
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pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
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printf (" PCIE1 connected to ULI as %s (base addr %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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} else {
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printf (" PCIE1: disabled\n");
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}
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puts("\n");
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#else
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setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE1); /* disable */
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#endif
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#ifdef CONFIG_PCIE2
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pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
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if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){
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SET_STD_PCIE_INFO(pci_info[num], 2);
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pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
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printf (" PCIE2 connected to Slot as %s (base addr %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie2_hose, first_free_busno);
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} else {
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printf (" PCIE2: disabled\n");
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}
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puts("\n");
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#else
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setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE2); /* disable */
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#endif
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#ifdef CONFIG_PCI1
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if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
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SET_STD_PCI_INFO(pci_info[num], 1);
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pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
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printf(" PCI connected to PCI slots as %s" \
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" (base address %lx)\n",
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pci_agent ? "Agent" : "Host",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pci1_hose, first_free_busno);
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} else {
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printf (" PCI: disabled\n");
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}
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puts("\n");
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#else
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setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
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#endif
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void
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ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI1
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ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
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#endif
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#ifdef CONFIG_PCIE1
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ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
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#endif
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#ifdef CONFIG_PCIE2
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ft_fsl_pci_setup(blob, "pci2", &pcie2_hose);
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#endif
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}
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#endif
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/*
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* get_board_sys_clk
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* Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
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*/
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unsigned long
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get_board_sys_clk(ulong dummy)
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{
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u8 i;
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ulong val = 0;
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u8 *pixis_base = (u8 *)PIXIS_BASE;
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i = in_8(pixis_base + PIXIS_SPD);
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i &= 0x07;
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switch (i) {
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case 0:
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val = 33333000;
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break;
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case 1:
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val = 39999600;
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break;
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case 2:
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val = 49999500;
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break;
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case 3:
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val = 66666000;
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break;
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case 4:
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val = 83332500;
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break;
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case 5:
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val = 99999000;
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break;
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case 6:
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val = 133332000;
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break;
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case 7:
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val = 166665000;
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break;
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}
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return val;
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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void board_reset(void)
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{
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u8 *pixis_base = (u8 *)PIXIS_BASE;
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out_8(pixis_base + PIXIS_RST, 0);
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while (1)
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;
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}
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