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![Timur Tabi](/assets/img/avatar_default.png)
Refactor and document the Freescale PIXIS code, used on most 85xx and 86xx boards. This makes the code easier to read and more flexible. Delete pixis.h, because none of the exported functions were actually being used by any other file. Make all of the functions in pixis.c 'static'. Remove "#include pixis.h" from every file that has it. Remove some unnecessary #includes. Make 'pixis_base' into a macro, so that we don't need to define it in every function. Add "while(1);" loops at the end of functions that reset the board, so that execution doesn't continue while the reset is in progress. Replace in_8/out_8 calls with clrbits_8, setbits_8, or clrsetbits_8, where appropriate. Replace ulong/uint with their spelled-out equivalents. Remove unnecessary typecasts, changing the types of some variables if necessary. Add CONFIG_SYS_PIXIS_VCFGEN0_ENABLE and CONFIG_SYS_PIXIS_VBOOT_ENABLE to make it easier for specific boards to support variations in the PIXIS registers sets. No current boards appears to need this feature. Fix the definition of CONFIG_SYS_PIXIS_VBOOT_MASK for the MPC8610 HPCD. Apparently, "pixis_reset altbank" has never worked on this board. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
558 lines
13 KiB
C
558 lines
13 KiB
C
/*
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* Copyright 2008-2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <spd.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <spd_sdram.h>
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#include <fdt_support.h>
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#include <tsec.h>
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#include <netdev.h>
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#include <sata.h>
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#include "../common/sgmii_riser.h"
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phys_size_t fixed_sdram(void);
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int board_early_init_f (void)
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{
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#ifdef CONFIG_MMC
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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setbits_be32(&gur->pmuxcr,
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(MPC85xx_PMUXCR_SD_DATA |
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MPC85xx_PMUXCR_SDHC_CD |
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MPC85xx_PMUXCR_SDHC_WP));
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#endif
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return 0;
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}
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int checkboard (void)
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{
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u8 vboot;
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u8 *pixis_base = (u8 *)PIXIS_BASE;
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puts("Board: MPC8536DS ");
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#ifdef CONFIG_PHYS_64BIT
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puts("(36-bit addrmap) ");
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#endif
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printf ("Sys ID: 0x%02x, "
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"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
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in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
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in_8(pixis_base + PIXIS_PVER));
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vboot = in_8(pixis_base + PIXIS_VBOOT);
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switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
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case PIXIS_VBOOT_LBMAP_NOR0:
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puts ("vBank: 0\n");
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break;
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case PIXIS_VBOOT_LBMAP_NOR1:
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puts ("vBank: 1\n");
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break;
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case PIXIS_VBOOT_LBMAP_NOR2:
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puts ("vBank: 2\n");
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break;
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case PIXIS_VBOOT_LBMAP_NOR3:
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puts ("vBank: 3\n");
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break;
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case PIXIS_VBOOT_LBMAP_PJET:
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puts ("Promjet\n");
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break;
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case PIXIS_VBOOT_LBMAP_NAND:
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puts ("NAND\n");
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break;
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}
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return 0;
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}
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phys_size_t
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initdram(int board_type)
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{
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phys_size_t dram_size = 0;
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puts("Initializing....");
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#ifdef CONFIG_SPD_EEPROM
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dram_size = fsl_ddr_sdram();
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#else
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dram_size = fixed_sdram();
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#endif
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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puts(" DDR: ");
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return dram_size;
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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phys_size_t fixed_sdram (void)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile ccsr_ddr_t *ddr= &immap->im_ddr;
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uint d_init;
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ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
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ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
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ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
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ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
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ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
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ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
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ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
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#if defined (CONFIG_DDR_ECC)
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ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
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ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
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ddr->err_sbe = CONFIG_SYS_DDR_SBE;
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#endif
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asm("sync;isync");
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udelay(500);
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ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
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#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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d_init = 1;
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debug("DDR - 1st controller: memory initializing\n");
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/*
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* Poll until memory is initialized.
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* 512 Meg at 400 might hit this 200 times or so.
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*/
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while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
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udelay(1000);
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}
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debug("DDR: memory initialized\n\n");
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asm("sync; isync");
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udelay(500);
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#endif
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return 512 * 1024 * 1024;
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}
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#endif
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#ifdef CONFIG_PCI1
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static struct pci_controller pci1_hose;
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#endif
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif
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#ifdef CONFIG_PCIE2
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static struct pci_controller pcie2_hose;
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#endif
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#ifdef CONFIG_PCIE3
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static struct pci_controller pcie3_hose;
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#endif
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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struct fsl_pci_info pci_info[4];
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u32 devdisr, pordevsr, io_sel, sdrs2_io_sel;
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u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
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int first_free_busno = 0;
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int num = 0;
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int pcie_ep, pcie_configured;
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devdisr = in_be32(&gur->devdisr);
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pordevsr = in_be32(&gur->pordevsr);
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porpllsr = in_be32(&gur->porpllsr);
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io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
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sdrs2_io_sel = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
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debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x\n",
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devdisr, sdrs2_io_sel, io_sel);
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if (sdrs2_io_sel == 7)
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printf(" Serdes2 disalbed\n");
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else if (sdrs2_io_sel == 4) {
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printf(" eTSEC1 is in sgmii mode.\n");
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printf(" eTSEC3 is in sgmii mode.\n");
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} else if (sdrs2_io_sel == 6)
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printf(" eTSEC1 is in sgmii mode.\n");
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puts("\n");
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#ifdef CONFIG_PCIE3
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pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
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SET_STD_PCIE_INFO(pci_info[num], 3);
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pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
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printf (" PCIE3 connected to Slot3 as %s (base address %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie3_hose, first_free_busno);
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} else {
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printf (" PCIE3: disabled\n");
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}
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puts("\n");
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
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#endif
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#ifdef CONFIG_PCIE1
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pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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SET_STD_PCIE_INFO(pci_info[num], 1);
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pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
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printf (" PCIE1 connected to Slot1 as %s (base address %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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} else {
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printf (" PCIE1: disabled\n");
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}
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puts("\n");
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
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#endif
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#ifdef CONFIG_PCIE2
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pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
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SET_STD_PCIE_INFO(pci_info[num], 2);
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pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
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printf (" PCIE2 connected to Slot 2 as %s (base address %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie2_hose, first_free_busno);
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} else {
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printf (" PCIE2: disabled\n");
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}
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puts("\n");
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
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#endif
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#ifdef CONFIG_PCI1
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pci_speed = 66666000;
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pci_32 = 1;
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pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
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pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
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SET_STD_PCI_INFO(pci_info[num], 1);
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pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
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printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
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(pci_32) ? 32 : 64,
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(pci_speed == 33333000) ? "33" :
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(pci_speed == 66666000) ? "66" : "unknown",
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pci_clk_sel ? "sync" : "async",
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pci_agent ? "agent" : "host",
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pci_arb ? "arbiter" : "external-arbiter",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pci1_hose, first_free_busno);
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} else {
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printf (" PCI: disabled\n");
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}
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puts("\n");
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
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#endif
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}
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#endif
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash + PROMJET region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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/* invalidate existing TLB entry for flash + promjet */
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disable_tlb(flash_esel);
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
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0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
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return 0;
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}
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#ifdef CONFIG_GET_CLK_FROM_ICS307
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/* decode S[0-2] to Output Divider (OD) */
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static unsigned char
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ics307_S_to_OD[] = {
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10, 2, 8, 4, 5, 7, 3, 6
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};
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/* Calculate frequency being generated by ICS307-02 clock chip based upon
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* the control bytes being programmed into it. */
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/* XXX: This function should probably go into a common library */
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static unsigned long
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ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
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{
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const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
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unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
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unsigned long RDW = cw2 & 0x7F;
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unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
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unsigned long freq;
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/* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
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/* cw0: C1 C0 TTL F1 F0 S2 S1 S0
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* cw1: V8 V7 V6 V5 V4 V3 V2 V1
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* cw2: V0 R6 R5 R4 R3 R2 R1 R0
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*
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* R6:R0 = Reference Divider Word (RDW)
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* V8:V0 = VCO Divider Word (VDW)
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* S2:S0 = Output Divider Select (OD)
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* F1:F0 = Function of CLK2 Output
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* TTL = duty cycle
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* C1:C0 = internal load capacitance for cyrstal
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*/
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/* Adding 1 to get a "nicely" rounded number, but this needs
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* more tweaking to get a "properly" rounded number. */
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freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
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debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
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freq);
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return freq;
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}
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unsigned long
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get_board_sys_clk(ulong dummy)
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{
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u8 *pixis_base = (u8 *)PIXIS_BASE;
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return ics307_clk_freq (
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in_8(pixis_base + PIXIS_VSYSCLK0),
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in_8(pixis_base + PIXIS_VSYSCLK1),
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in_8(pixis_base + PIXIS_VSYSCLK2)
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);
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}
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unsigned long
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get_board_ddr_clk(ulong dummy)
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{
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u8 *pixis_base = (u8 *)PIXIS_BASE;
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return ics307_clk_freq (
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in_8(pixis_base + PIXIS_VDDRCLK0),
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in_8(pixis_base + PIXIS_VDDRCLK1),
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in_8(pixis_base + PIXIS_VDDRCLK2)
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);
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}
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#else
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unsigned long
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get_board_sys_clk(ulong dummy)
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{
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u8 i;
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ulong val = 0;
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u8 *pixis_base = (u8 *)PIXIS_BASE;
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i = in_8(pixis_base + PIXIS_SPD);
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i &= 0x07;
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switch (i) {
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case 0:
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val = 33333333;
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break;
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case 1:
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val = 40000000;
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break;
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case 2:
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val = 50000000;
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break;
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case 3:
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val = 66666666;
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break;
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case 4:
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val = 83333333;
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break;
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case 5:
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val = 100000000;
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break;
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case 6:
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val = 133333333;
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break;
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case 7:
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val = 166666666;
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break;
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}
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return val;
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}
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unsigned long
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get_board_ddr_clk(ulong dummy)
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{
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u8 i;
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ulong val = 0;
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u8 *pixis_base = (u8 *)PIXIS_BASE;
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i = in_8(pixis_base + PIXIS_SPD);
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i &= 0x38;
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i >>= 3;
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switch (i) {
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case 0:
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|
val = 33333333;
|
|
break;
|
|
case 1:
|
|
val = 40000000;
|
|
break;
|
|
case 2:
|
|
val = 50000000;
|
|
break;
|
|
case 3:
|
|
val = 66666666;
|
|
break;
|
|
case 4:
|
|
val = 83333333;
|
|
break;
|
|
case 5:
|
|
val = 100000000;
|
|
break;
|
|
case 6:
|
|
val = 133333333;
|
|
break;
|
|
case 7:
|
|
val = 166666666;
|
|
break;
|
|
}
|
|
return val;
|
|
}
|
|
#endif
|
|
|
|
int sata_initialize(void)
|
|
{
|
|
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
|
uint sdrs2_io_sel =
|
|
(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
|
|
if (sdrs2_io_sel & 0x04)
|
|
return 1;
|
|
|
|
return __sata_initialize();
|
|
}
|
|
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
#ifdef CONFIG_TSEC_ENET
|
|
struct tsec_info_struct tsec_info[2];
|
|
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
|
int num = 0;
|
|
uint sdrs2_io_sel =
|
|
(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
|
|
|
|
#ifdef CONFIG_TSEC1
|
|
SET_STD_TSEC_INFO(tsec_info[num], 1);
|
|
if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) {
|
|
tsec_info[num].phyaddr = 0;
|
|
tsec_info[num].flags |= TSEC_SGMII;
|
|
}
|
|
num++;
|
|
#endif
|
|
#ifdef CONFIG_TSEC3
|
|
SET_STD_TSEC_INFO(tsec_info[num], 3);
|
|
if (sdrs2_io_sel == 4) {
|
|
tsec_info[num].phyaddr = 1;
|
|
tsec_info[num].flags |= TSEC_SGMII;
|
|
}
|
|
num++;
|
|
#endif
|
|
|
|
if (!num) {
|
|
printf("No TSECs initialized\n");
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_FSL_SGMII_RISER
|
|
if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6))
|
|
fsl_sgmii_riser_init(tsec_info, num);
|
|
#endif
|
|
|
|
tsec_eth_init(bis, tsec_info, num);
|
|
#endif
|
|
return pci_eth_init(bis);
|
|
}
|
|
|
|
#if defined(CONFIG_OF_BOARD_SETUP)
|
|
void ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
ft_cpu_setup(blob, bd);
|
|
|
|
#ifdef CONFIG_PCI1
|
|
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
|
|
#endif
|
|
#ifdef CONFIG_PCIE2
|
|
ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
|
|
#endif
|
|
#ifdef CONFIG_PCIE2
|
|
ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
|
|
#endif
|
|
#ifdef CONFIG_PCIE1
|
|
ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);
|
|
#endif
|
|
#ifdef CONFIG_FSL_SGMII_RISER
|
|
fsl_sgmii_riser_fdt_fixup(blob);
|
|
#endif
|
|
}
|
|
#endif
|