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https://github.com/brain-hackers/u-boot-brain
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![Peng Fan](/assets/img/avatar_default.png)
The USBNC_PHYCFG2_ACAENB bit should be cleared to enable the OTG ID detection, not set it. When the bit is set, the ACA Resistance Detection is enabled, which disables the OTG ID detection, because the internal pull up is off. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
362 lines
8.8 KiB
C
362 lines
8.8 KiB
C
/*
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* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
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* Copyright (C) 2010 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <usb.h>
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#include <errno.h>
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#include <wait_bit.h>
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#include <linux/compiler.h>
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#include <usb/ehci-ci.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/imx-common/iomux-v3.h>
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#include "ehci.h"
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#define USB_OTGREGS_OFFSET 0x000
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#define USB_H1REGS_OFFSET 0x200
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#define USB_H2REGS_OFFSET 0x400
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#define USB_H3REGS_OFFSET 0x600
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#define USB_OTHERREGS_OFFSET 0x800
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#define USB_H1_CTRL_OFFSET 0x04
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#define USBPHY_CTRL 0x00000030
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#define USBPHY_CTRL_SET 0x00000034
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#define USBPHY_CTRL_CLR 0x00000038
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#define USBPHY_CTRL_TOG 0x0000003c
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#define USBPHY_PWD 0x00000000
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#define USBPHY_CTRL_SFTRST 0x80000000
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#define USBPHY_CTRL_CLKGATE 0x40000000
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#define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
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#define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
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#define USBPHY_CTRL_OTG_ID 0x08000000
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#define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
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#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
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#define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
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#define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
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#define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
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#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
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#define USBNC_OFFSET 0x200
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#define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
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#define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
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#define UCTRL_PM (1 << 9) /* OTG Power Mask */
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#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
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#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
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/* USBCMD */
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#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
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#define UCMD_RESET (1 << 1) /* controller reset */
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#if defined(CONFIG_MX6)
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static const unsigned phy_bases[] = {
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USB_PHY0_BASE_ADDR,
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USB_PHY1_BASE_ADDR,
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};
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static void usb_internal_phy_clock_gate(int index, int on)
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{
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void __iomem *phy_reg;
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if (index >= ARRAY_SIZE(phy_bases))
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return;
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phy_reg = (void __iomem *)phy_bases[index];
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phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
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writel(USBPHY_CTRL_CLKGATE, phy_reg);
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}
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static void usb_power_config(int index)
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{
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struct anatop_regs __iomem *anatop =
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(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
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void __iomem *chrg_detect;
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void __iomem *pll_480_ctrl_clr;
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void __iomem *pll_480_ctrl_set;
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switch (index) {
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case 0:
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chrg_detect = &anatop->usb1_chrg_detect;
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pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
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pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
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break;
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case 1:
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chrg_detect = &anatop->usb2_chrg_detect;
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pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
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pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
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break;
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default:
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return;
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}
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/*
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* Some phy and power's special controls
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* 1. The external charger detector needs to be disabled
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* or the signal at DP will be poor
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* 2. The PLL's power and output to usb
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* is totally controlled by IC, so the Software only needs
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* to enable them at initializtion.
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*/
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writel(ANADIG_USB2_CHRG_DETECT_EN_B |
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ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
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chrg_detect);
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writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
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pll_480_ctrl_clr);
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writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
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ANADIG_USB2_PLL_480_CTRL_POWER |
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ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
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pll_480_ctrl_set);
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}
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/* Return 0 : host node, <>0 : device mode */
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static int usb_phy_enable(int index, struct usb_ehci *ehci)
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{
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void __iomem *phy_reg;
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void __iomem *phy_ctrl;
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void __iomem *usb_cmd;
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int ret;
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if (index >= ARRAY_SIZE(phy_bases))
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return 0;
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phy_reg = (void __iomem *)phy_bases[index];
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phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
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usb_cmd = (void __iomem *)&ehci->usbcmd;
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/* Stop then Reset */
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clrbits_le32(usb_cmd, UCMD_RUN_STOP);
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ret = wait_for_bit(__func__, usb_cmd, UCMD_RUN_STOP, false, 10000,
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false);
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if (ret)
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return ret;
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setbits_le32(usb_cmd, UCMD_RESET);
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ret = wait_for_bit(__func__, usb_cmd, UCMD_RESET, false, 10000, false);
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if (ret)
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return ret;
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/* Reset USBPHY module */
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setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
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udelay(10);
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/* Remove CLKGATE and SFTRST */
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clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
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udelay(10);
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/* Power up the PHY */
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writel(0, phy_reg + USBPHY_PWD);
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/* enable FS/LS device */
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setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
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USBPHY_CTRL_ENUTMILEVEL3);
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return 0;
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}
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int usb_phy_mode(int port)
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{
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void __iomem *phy_reg;
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void __iomem *phy_ctrl;
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u32 val;
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phy_reg = (void __iomem *)phy_bases[port];
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phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
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val = readl(phy_ctrl);
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if (val & USBPHY_CTRL_OTG_ID)
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return USB_INIT_DEVICE;
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else
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return USB_INIT_HOST;
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}
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/* Base address for this IP block is 0x02184800 */
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struct usbnc_regs {
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u32 ctrl[4]; /* otg/host1-3 */
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u32 uh2_hsic_ctrl;
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u32 uh3_hsic_ctrl;
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u32 otg_phy_ctrl_0;
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u32 uh1_phy_ctrl_0;
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};
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#elif defined(CONFIG_MX7)
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struct usbnc_regs {
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u32 ctrl1;
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u32 ctrl2;
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u32 reserve1[10];
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u32 phy_cfg1;
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u32 phy_cfg2;
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u32 reserve2;
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u32 phy_status;
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u32 reserve3[4];
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u32 adp_cfg1;
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u32 adp_cfg2;
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u32 adp_status;
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};
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static void usb_power_config(int index)
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{
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struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
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(0x10000 * index) + USBNC_OFFSET);
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void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
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/*
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* Clear the ACAENB to enable usb_otg_id detection,
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* otherwise it is the ACA detection enabled.
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*/
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clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
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}
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int usb_phy_mode(int port)
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{
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struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
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(0x10000 * port) + USBNC_OFFSET);
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void __iomem *status = (void __iomem *)(&usbnc->phy_status);
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u32 val;
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val = readl(status);
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if (val & USBNC_PHYSTATUS_ID_DIG)
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return USB_INIT_DEVICE;
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else
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return USB_INIT_HOST;
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}
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#endif
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static void usb_oc_config(int index)
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{
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#if defined(CONFIG_MX6)
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struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
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USB_OTHERREGS_OFFSET);
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void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
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#elif defined(CONFIG_MX7)
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struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
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(0x10000 * index) + USBNC_OFFSET);
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void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
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#endif
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#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
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/* mx6qarm2 seems to required a different setting*/
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clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
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#else
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setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
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#endif
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#if defined(CONFIG_MX6)
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setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
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#elif defined(CONFIG_MX7)
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setbits_le32(ctrl, UCTRL_OVER_CUR_DIS | UCTRL_PM);
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#endif
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}
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/**
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* board_usb_phy_mode - override usb phy mode
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* @port: usb host/otg port
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*
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* Target board specific, override usb_phy_mode.
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* When usb-otg is used as usb host port, iomux pad usb_otg_id can be
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* left disconnected in this case usb_phy_mode will not be able to identify
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* the phy mode that usb port is used.
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* Machine file overrides board_usb_phy_mode.
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*
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* Return: USB_INIT_DEVICE or USB_INIT_HOST
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*/
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int __weak board_usb_phy_mode(int port)
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{
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return usb_phy_mode(port);
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}
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/**
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* board_ehci_hcd_init - set usb vbus voltage
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* @port: usb otg port
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*
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* Target board specific, setup iomux pad to setup supply vbus voltage
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* for usb otg port. Machine board file overrides board_ehci_hcd_init
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*
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* Return: 0 Success
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*/
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int __weak board_ehci_hcd_init(int port)
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{
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return 0;
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}
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/**
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* board_ehci_power - enables/disables usb vbus voltage
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* @port: usb otg port
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* @on: on/off vbus voltage
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*
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* Enables/disables supply vbus voltage for usb otg port.
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* Machine board file overrides board_ehci_power
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*
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* Return: 0 Success
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*/
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int __weak board_ehci_power(int port, int on)
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{
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return 0;
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}
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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enum usb_init_type type;
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#if defined(CONFIG_MX6)
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u32 controller_spacing = 0x200;
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#elif defined(CONFIG_MX7)
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u32 controller_spacing = 0x10000;
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#endif
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struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
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(controller_spacing * index));
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int ret;
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if (index > 3)
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return -EINVAL;
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enable_usboh3_clk(1);
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mdelay(1);
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/* Do board specific initialization */
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ret = board_ehci_hcd_init(index);
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if (ret)
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return ret;
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usb_power_config(index);
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usb_oc_config(index);
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#if defined(CONFIG_MX6)
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usb_internal_phy_clock_gate(index, 1);
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usb_phy_enable(index, ehci);
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#endif
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type = board_usb_phy_mode(index);
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*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
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*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
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HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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if ((type == init) || (type == USB_INIT_DEVICE))
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board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
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if (type != init)
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return -ENODEV;
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if (type == USB_INIT_DEVICE)
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return 0;
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setbits_le32(&ehci->usbmode, CM_HOST);
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writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
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setbits_le32(&ehci->portsc, USB_EN);
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mdelay(10);
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return 0;
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}
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int ehci_hcd_stop(int index)
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{
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return 0;
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}
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