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https://github.com/brain-hackers/u-boot-brain
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![Alexey Brodkin](/assets/img/avatar_default.png)
Commit 90b7fc924a
"net: designware: support phy reset device-tree
bindings" made DW GMAC driver dependent on DM_GPIO by unconditional
usage of purely DM_GPIO stuff like:
* dm_gpio_XXX()
* gpio_request_by_name()
But since that driver as of today might be easily used without
DM_GPIO (that's the case for Synopsys AXS10x boards) we're
shielding all DM_GPIO things by ifdefs.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Beniamino Galvani <b.galvani@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Cc: Sonic Zhang <sonic.zhang@analog.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
255 lines
6.3 KiB
C
255 lines
6.3 KiB
C
/*
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* (C) Copyright 2010
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _DW_ETH_H
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#define _DW_ETH_H
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#ifdef CONFIG_DM_GPIO
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#include <asm-generic/gpio.h>
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#endif
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#define CONFIG_TX_DESCR_NUM 16
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#define CONFIG_RX_DESCR_NUM 16
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#define CONFIG_ETH_BUFSIZE 2048
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#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
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#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
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#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
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#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
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struct eth_mac_regs {
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u32 conf; /* 0x00 */
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u32 framefilt; /* 0x04 */
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u32 hashtablehigh; /* 0x08 */
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u32 hashtablelow; /* 0x0c */
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u32 miiaddr; /* 0x10 */
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u32 miidata; /* 0x14 */
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u32 flowcontrol; /* 0x18 */
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u32 vlantag; /* 0x1c */
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u32 version; /* 0x20 */
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u8 reserved_1[20];
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u32 intreg; /* 0x38 */
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u32 intmask; /* 0x3c */
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u32 macaddr0hi; /* 0x40 */
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u32 macaddr0lo; /* 0x44 */
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};
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/* MAC configuration register definitions */
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#define FRAMEBURSTENABLE (1 << 21)
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#define MII_PORTSELECT (1 << 15)
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#define FES_100 (1 << 14)
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#define DISABLERXOWN (1 << 13)
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#define FULLDPLXMODE (1 << 11)
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#define RXENABLE (1 << 2)
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#define TXENABLE (1 << 3)
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/* MII address register definitions */
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#define MII_BUSY (1 << 0)
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#define MII_WRITE (1 << 1)
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#define MII_CLKRANGE_60_100M (0)
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#define MII_CLKRANGE_100_150M (0x4)
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#define MII_CLKRANGE_20_35M (0x8)
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#define MII_CLKRANGE_35_60M (0xC)
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#define MII_CLKRANGE_150_250M (0x10)
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#define MII_CLKRANGE_250_300M (0x14)
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#define MIIADDRSHIFT (11)
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#define MIIREGSHIFT (6)
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#define MII_REGMSK (0x1F << 6)
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#define MII_ADDRMSK (0x1F << 11)
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struct eth_dma_regs {
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u32 busmode; /* 0x00 */
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u32 txpolldemand; /* 0x04 */
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u32 rxpolldemand; /* 0x08 */
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u32 rxdesclistaddr; /* 0x0c */
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u32 txdesclistaddr; /* 0x10 */
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u32 status; /* 0x14 */
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u32 opmode; /* 0x18 */
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u32 intenable; /* 0x1c */
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u32 reserved1[2];
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u32 axibus; /* 0x28 */
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u32 reserved2[7];
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u32 currhosttxdesc; /* 0x48 */
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u32 currhostrxdesc; /* 0x4c */
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u32 currhosttxbuffaddr; /* 0x50 */
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u32 currhostrxbuffaddr; /* 0x54 */
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};
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#define DW_DMA_BASE_OFFSET (0x1000)
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/* Default DMA Burst length */
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#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL
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#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8
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#endif
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/* Bus mode register definitions */
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#define FIXEDBURST (1 << 16)
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#define PRIORXTX_41 (3 << 14)
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#define PRIORXTX_31 (2 << 14)
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#define PRIORXTX_21 (1 << 14)
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#define PRIORXTX_11 (0 << 14)
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#define DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8)
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#define RXHIGHPRIO (1 << 1)
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#define DMAMAC_SRST (1 << 0)
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/* Poll demand definitions */
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#define POLL_DATA (0xFFFFFFFF)
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/* Operation mode definitions */
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#define STOREFORWARD (1 << 21)
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#define FLUSHTXFIFO (1 << 20)
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#define TXSTART (1 << 13)
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#define TXSECONDFRAME (1 << 2)
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#define RXSTART (1 << 1)
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/* Descriptior related definitions */
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#define MAC_MAX_FRAME_SZ (1600)
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struct dmamacdescr {
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u32 txrx_status;
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u32 dmamac_cntl;
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u32 dmamac_addr;
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u32 dmamac_next;
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} __aligned(ARCH_DMA_MINALIGN);
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/*
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* txrx_status definitions
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*/
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/* tx status bits definitions */
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#if defined(CONFIG_DW_ALTDESCRIPTOR)
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#define DESC_TXSTS_OWNBYDMA (1 << 31)
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#define DESC_TXSTS_TXINT (1 << 30)
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#define DESC_TXSTS_TXLAST (1 << 29)
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#define DESC_TXSTS_TXFIRST (1 << 28)
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#define DESC_TXSTS_TXCRCDIS (1 << 27)
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#define DESC_TXSTS_TXPADDIS (1 << 26)
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#define DESC_TXSTS_TXCHECKINSCTRL (3 << 22)
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#define DESC_TXSTS_TXRINGEND (1 << 21)
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#define DESC_TXSTS_TXCHAIN (1 << 20)
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#define DESC_TXSTS_MSK (0x1FFFF << 0)
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#else
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#define DESC_TXSTS_OWNBYDMA (1 << 31)
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#define DESC_TXSTS_MSK (0x1FFFF << 0)
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#endif
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/* rx status bits definitions */
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#define DESC_RXSTS_OWNBYDMA (1 << 31)
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#define DESC_RXSTS_DAFILTERFAIL (1 << 30)
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#define DESC_RXSTS_FRMLENMSK (0x3FFF << 16)
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#define DESC_RXSTS_FRMLENSHFT (16)
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#define DESC_RXSTS_ERROR (1 << 15)
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#define DESC_RXSTS_RXTRUNCATED (1 << 14)
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#define DESC_RXSTS_SAFILTERFAIL (1 << 13)
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#define DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12)
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#define DESC_RXSTS_RXDAMAGED (1 << 11)
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#define DESC_RXSTS_RXVLANTAG (1 << 10)
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#define DESC_RXSTS_RXFIRST (1 << 9)
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#define DESC_RXSTS_RXLAST (1 << 8)
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#define DESC_RXSTS_RXIPC_GIANT (1 << 7)
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#define DESC_RXSTS_RXCOLLISION (1 << 6)
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#define DESC_RXSTS_RXFRAMEETHER (1 << 5)
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#define DESC_RXSTS_RXWATCHDOG (1 << 4)
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#define DESC_RXSTS_RXMIIERROR (1 << 3)
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#define DESC_RXSTS_RXDRIBBLING (1 << 2)
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#define DESC_RXSTS_RXCRC (1 << 1)
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/*
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* dmamac_cntl definitions
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*/
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/* tx control bits definitions */
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#if defined(CONFIG_DW_ALTDESCRIPTOR)
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#define DESC_TXCTRL_SIZE1MASK (0x1FFF << 0)
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#define DESC_TXCTRL_SIZE1SHFT (0)
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#define DESC_TXCTRL_SIZE2MASK (0x1FFF << 16)
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#define DESC_TXCTRL_SIZE2SHFT (16)
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#else
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#define DESC_TXCTRL_TXINT (1 << 31)
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#define DESC_TXCTRL_TXLAST (1 << 30)
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#define DESC_TXCTRL_TXFIRST (1 << 29)
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#define DESC_TXCTRL_TXCHECKINSCTRL (3 << 27)
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#define DESC_TXCTRL_TXCRCDIS (1 << 26)
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#define DESC_TXCTRL_TXRINGEND (1 << 25)
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#define DESC_TXCTRL_TXCHAIN (1 << 24)
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#define DESC_TXCTRL_SIZE1MASK (0x7FF << 0)
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#define DESC_TXCTRL_SIZE1SHFT (0)
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#define DESC_TXCTRL_SIZE2MASK (0x7FF << 11)
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#define DESC_TXCTRL_SIZE2SHFT (11)
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#endif
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/* rx control bits definitions */
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#if defined(CONFIG_DW_ALTDESCRIPTOR)
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#define DESC_RXCTRL_RXINTDIS (1 << 31)
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#define DESC_RXCTRL_RXRINGEND (1 << 15)
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#define DESC_RXCTRL_RXCHAIN (1 << 14)
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#define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0)
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#define DESC_RXCTRL_SIZE1SHFT (0)
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#define DESC_RXCTRL_SIZE2MASK (0x1FFF << 16)
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#define DESC_RXCTRL_SIZE2SHFT (16)
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#else
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#define DESC_RXCTRL_RXINTDIS (1 << 31)
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#define DESC_RXCTRL_RXRINGEND (1 << 25)
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#define DESC_RXCTRL_RXCHAIN (1 << 24)
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#define DESC_RXCTRL_SIZE1MASK (0x7FF << 0)
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#define DESC_RXCTRL_SIZE1SHFT (0)
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#define DESC_RXCTRL_SIZE2MASK (0x7FF << 11)
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#define DESC_RXCTRL_SIZE2SHFT (11)
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#endif
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struct dw_eth_dev {
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struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
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struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
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char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
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char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
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u32 interface;
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u32 max_speed;
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u32 tx_currdescnum;
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u32 rx_currdescnum;
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struct eth_mac_regs *mac_regs_p;
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struct eth_dma_regs *dma_regs_p;
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#ifndef CONFIG_DM_ETH
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struct eth_device *dev;
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#endif
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#ifdef CONFIG_DM_GPIO
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struct gpio_desc reset_gpio;
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#endif
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struct phy_device *phydev;
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struct mii_dev *bus;
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};
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#ifdef CONFIG_DM_ETH
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struct dw_eth_pdata {
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struct eth_pdata eth_pdata;
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u32 reset_delays[3];
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};
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#endif
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#endif
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