mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-16 23:18:51 +09:00
![Stephen Warren](/assets/img/avatar_default.png)
The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
189 lines
4.2 KiB
C
189 lines
4.2 KiB
C
/*
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* Copyright (c) 2013 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dwmmc.h>
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#include <errno.h>
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#include <pwrseq.h>
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#include <syscon.h>
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#include <asm/gpio.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/periph.h>
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#include <linux/err.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct rockchip_mmc_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct rockchip_dwmmc_priv {
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struct clk clk;
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struct dwmci_host host;
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};
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static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
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{
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struct udevice *dev = host->priv;
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struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
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int ret;
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ret = clk_set_rate(&priv->clk, freq);
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if (ret < 0) {
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debug("%s: err=%d\n", __func__, ret);
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return ret;
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}
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return freq;
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}
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static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
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{
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struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
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struct dwmci_host *host = &priv->host;
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host->name = dev->name;
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host->ioaddr = (void *)dev_get_addr(dev);
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host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
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"bus-width", 4);
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host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
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host->priv = dev;
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/* use non-removeable as sdcard and emmc as judgement */
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if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "non-removable"))
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host->dev_index = 0;
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else
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host->dev_index = 1;
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return 0;
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}
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static int rockchip_dwmmc_probe(struct udevice *dev)
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{
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#ifdef CONFIG_BLK
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struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
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#endif
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
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struct dwmci_host *host = &priv->host;
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struct udevice *pwr_dev __maybe_unused;
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u32 minmax[2];
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int ret;
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int fifo_depth;
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret < 0)
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return ret;
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if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
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"clock-freq-min-max", minmax, 2))
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return -EINVAL;
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fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
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"fifo-depth", 0);
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if (fifo_depth < 0)
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return -EINVAL;
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host->fifoth_val = MSIZE(0x2) |
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RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
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if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "fifo-mode"))
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host->fifo_mode = true;
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#ifdef CONFIG_PWRSEQ
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/* Enable power if needed */
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ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
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&pwr_dev);
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if (!ret) {
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ret = pwrseq_set_power(pwr_dev, true);
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if (ret)
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return ret;
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}
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#endif
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#ifdef CONFIG_BLK
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dwmci_setup_cfg(&plat->cfg, dev->name, host->buswidth, host->caps,
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minmax[1], minmax[0]);
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host->mmc = &plat->mmc;
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#else
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ret = add_dwmci(host, minmax[1], minmax[0]);
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if (ret)
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return ret;
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#endif
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host->mmc->priv = &priv->host;
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host->mmc->dev = dev;
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upriv->mmc = host->mmc;
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return 0;
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}
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static int rockchip_dwmmc_bind(struct udevice *dev)
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{
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#ifdef CONFIG_BLK
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struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
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int ret;
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ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
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if (ret)
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return ret;
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#endif
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return 0;
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}
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static const struct udevice_id rockchip_dwmmc_ids[] = {
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{ .compatible = "rockchip,rk3288-dw-mshc" },
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{ }
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};
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U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
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.name = "rockchip_dwmmc",
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.id = UCLASS_MMC,
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.of_match = rockchip_dwmmc_ids,
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.ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
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.bind = rockchip_dwmmc_bind,
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.probe = rockchip_dwmmc_probe,
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.priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
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.platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
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};
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#ifdef CONFIG_PWRSEQ
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static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable)
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{
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struct gpio_desc reset;
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int ret;
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ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
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if (ret)
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return ret;
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dm_gpio_set_value(&reset, 1);
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udelay(1);
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dm_gpio_set_value(&reset, 0);
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udelay(200);
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return 0;
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}
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static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = {
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.set_power = rockchip_dwmmc_pwrseq_set_power,
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};
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static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = {
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{ .compatible = "mmc-pwrseq-emmc" },
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{ }
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};
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U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = {
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.name = "mmc_pwrseq_emmc",
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.id = UCLASS_PWRSEQ,
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.of_match = rockchip_dwmmc_pwrseq_ids,
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.ops = &rockchip_dwmmc_pwrseq_ops,
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};
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#endif
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