mirror of
https://github.com/brain-hackers/u-boot-brain
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![Stephen Warren](/assets/img/avatar_default.png)
The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
825 lines
21 KiB
C
825 lines
21 KiB
C
/*
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* (C) Copyright 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk3288.h>
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#include <asm/arch/grf_rk3288.h>
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#include <asm/arch/hardware.h>
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#include <dt-bindings/clock/rk3288-cru.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dm/uclass-internal.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct rk3288_clk_priv {
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struct rk3288_grf *grf;
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struct rk3288_cru *cru;
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ulong rate;
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};
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struct pll_div {
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u32 nr;
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u32 nf;
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u32 no;
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};
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enum {
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VCO_MAX_HZ = 2200U * 1000000,
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VCO_MIN_HZ = 440 * 1000000,
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OUTPUT_MAX_HZ = 2200U * 1000000,
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OUTPUT_MIN_HZ = 27500000,
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FREF_MAX_HZ = 2200U * 1000000,
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FREF_MIN_HZ = 269 * 1000000,
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};
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enum {
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/* PLL CON0 */
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PLL_OD_MASK = 0x0f,
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/* PLL CON1 */
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PLL_NF_MASK = 0x1fff,
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/* PLL CON2 */
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PLL_BWADJ_MASK = 0x0fff,
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/* PLL CON3 */
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PLL_RESET_SHIFT = 5,
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/* CLKSEL0 */
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CORE_SEL_PLL_MASK = 1,
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CORE_SEL_PLL_SHIFT = 15,
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A17_DIV_MASK = 0x1f,
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A17_DIV_SHIFT = 8,
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MP_DIV_MASK = 0xf,
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MP_DIV_SHIFT = 4,
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M0_DIV_MASK = 0xf,
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M0_DIV_SHIFT = 0,
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/* CLKSEL1: pd bus clk pll sel: codec or general */
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PD_BUS_SEL_PLL_MASK = 15,
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PD_BUS_SEL_CPLL = 0,
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PD_BUS_SEL_GPLL,
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/* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
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PD_BUS_PCLK_DIV_SHIFT = 12,
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PD_BUS_PCLK_DIV_MASK = 7,
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/* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
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PD_BUS_HCLK_DIV_SHIFT = 8,
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PD_BUS_HCLK_DIV_MASK = 3,
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/* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
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PD_BUS_ACLK_DIV0_SHIFT = 3,
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PD_BUS_ACLK_DIV0_MASK = 0x1f,
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PD_BUS_ACLK_DIV1_SHIFT = 0,
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PD_BUS_ACLK_DIV1_MASK = 0x7,
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/*
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* CLKSEL10
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* peripheral bus pclk div:
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* aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
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*/
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PERI_SEL_PLL_MASK = 1,
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PERI_SEL_PLL_SHIFT = 15,
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PERI_SEL_CPLL = 0,
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PERI_SEL_GPLL,
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PERI_PCLK_DIV_SHIFT = 12,
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PERI_PCLK_DIV_MASK = 3,
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/* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
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PERI_HCLK_DIV_SHIFT = 8,
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PERI_HCLK_DIV_MASK = 3,
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/*
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* peripheral bus aclk div:
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* aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
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*/
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PERI_ACLK_DIV_SHIFT = 0,
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PERI_ACLK_DIV_MASK = 0x1f,
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SOCSTS_DPLL_LOCK = 1 << 5,
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SOCSTS_APLL_LOCK = 1 << 6,
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SOCSTS_CPLL_LOCK = 1 << 7,
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SOCSTS_GPLL_LOCK = 1 << 8,
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SOCSTS_NPLL_LOCK = 1 << 9,
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};
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#define RATE_TO_DIV(input_rate, output_rate) \
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((input_rate) / (output_rate) - 1);
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#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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#define PLL_DIVISORS(hz, _nr, _no) {\
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.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
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_Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
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(_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
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"divisors on line " __stringify(__LINE__));
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/* Keep divisors as low as possible to reduce jitter and power usage */
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static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
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static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
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void *rockchip_get_cru(void)
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{
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struct rk3288_clk_priv *priv;
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struct udevice *dev;
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int ret;
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ret = uclass_get_device(UCLASS_CLK, 0, &dev);
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if (ret)
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return ERR_PTR(ret);
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priv = dev_get_priv(dev);
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return priv->cru;
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}
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static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
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const struct pll_div *div)
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{
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int pll_id = rk_pll_id(clk_id);
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struct rk3288_pll *pll = &cru->pll[pll_id];
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/* All PLLs have same VCO and output frequency range restrictions. */
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uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
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uint output_hz = vco_hz / div->no;
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debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
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(uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
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assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
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output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
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(div->no == 1 || !(div->no % 2)));
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/* enter reset */
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rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
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rk_clrsetreg(&pll->con0,
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CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
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((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
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rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
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rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
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udelay(10);
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/* return from reset */
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rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
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return 0;
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}
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static inline unsigned int log2(unsigned int value)
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{
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return fls(value) - 1;
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}
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static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
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unsigned int hz)
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{
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static const struct pll_div dpll_cfg[] = {
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{.nf = 25, .nr = 2, .no = 1},
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{.nf = 400, .nr = 9, .no = 2},
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{.nf = 500, .nr = 9, .no = 2},
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{.nf = 100, .nr = 3, .no = 1},
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};
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int cfg;
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switch (hz) {
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case 300000000:
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cfg = 0;
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break;
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case 533000000: /* actually 533.3P MHz */
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cfg = 1;
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break;
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case 666000000: /* actually 666.6P MHz */
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cfg = 2;
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break;
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case 800000000:
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cfg = 3;
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break;
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default:
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debug("Unsupported SDRAM frequency");
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return -EINVAL;
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}
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/* pll enter slow-mode */
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rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
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DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
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rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
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/* wait for pll lock */
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while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
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udelay(1);
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/* PLL enter normal-mode */
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rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
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DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
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return 0;
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}
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#ifndef CONFIG_SPL_BUILD
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#define VCO_MAX_KHZ 2200000
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#define VCO_MIN_KHZ 440000
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#define FREF_MAX_KHZ 2200000
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#define FREF_MIN_KHZ 269
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static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
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{
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uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
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uint fref_khz;
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uint diff_khz, best_diff_khz;
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const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
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uint vco_khz;
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uint no = 1;
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uint freq_khz = freq_hz / 1000;
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if (!freq_hz) {
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printf("%s: the frequency can not be 0 Hz\n", __func__);
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return -EINVAL;
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}
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no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
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if (ext_div) {
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*ext_div = DIV_ROUND_UP(no, max_no);
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no = DIV_ROUND_UP(no, *ext_div);
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}
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/* only even divisors (and 1) are supported */
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if (no > 1)
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no = DIV_ROUND_UP(no, 2) * 2;
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vco_khz = freq_khz * no;
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if (ext_div)
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vco_khz *= *ext_div;
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if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
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printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
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__func__, freq_hz);
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return -1;
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}
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div->no = no;
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best_diff_khz = vco_khz;
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for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
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fref_khz = ref_khz / nr;
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if (fref_khz < FREF_MIN_KHZ)
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break;
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if (fref_khz > FREF_MAX_KHZ)
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continue;
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nf = vco_khz / fref_khz;
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if (nf >= max_nf)
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continue;
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diff_khz = vco_khz - nf * fref_khz;
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if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
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nf++;
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diff_khz = fref_khz - diff_khz;
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}
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if (diff_khz >= best_diff_khz)
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continue;
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best_diff_khz = diff_khz;
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div->nr = nr;
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div->nf = nf;
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}
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if (best_diff_khz > 4 * 1000) {
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printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
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__func__, freq_hz, best_diff_khz * 1000);
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return -EINVAL;
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}
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return 0;
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}
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static int rockchip_mac_set_clk(struct rk3288_cru *cru,
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int periph, uint freq)
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{
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/* Assuming mac_clk is fed by an external clock */
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rk_clrsetreg(&cru->cru_clksel_con[21],
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RMII_EXTCLK_MASK << RMII_EXTCLK_SHIFT,
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RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
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return 0;
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}
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static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
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int periph, unsigned int rate_hz)
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{
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struct pll_div npll_config = {0};
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u32 lcdc_div;
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int ret;
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ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
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if (ret)
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return ret;
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rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
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NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
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rkclk_set_pll(cru, CLK_NEW, &npll_config);
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/* waiting for pll lock */
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while (1) {
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if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
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break;
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udelay(1);
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}
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rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
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NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
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/* vop dclk source clk: npll,dclk_div: 1 */
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switch (periph) {
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case DCLK_VOP0:
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rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
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(lcdc_div - 1) << 8 | 2 << 0);
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break;
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case DCLK_VOP1:
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rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
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(lcdc_div - 1) << 8 | 2 << 6);
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break;
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}
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return 0;
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}
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#endif
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#ifdef CONFIG_SPL_BUILD
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static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
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{
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u32 aclk_div;
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u32 hclk_div;
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u32 pclk_div;
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/* pll enter slow-mode */
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rk_clrsetreg(&cru->cru_mode_con,
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GPLL_MODE_MASK << GPLL_MODE_SHIFT |
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CPLL_MODE_MASK << CPLL_MODE_SHIFT,
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GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
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CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
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/* init pll */
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rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
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rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
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/* waiting for pll lock */
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while ((readl(&grf->soc_status[1]) &
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(SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
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(SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
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udelay(1);
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/*
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* pd_bus clock pll source selection and
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* set up dependent divisors for PCLK/HCLK and ACLK clocks.
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*/
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aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
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assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
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hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
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assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
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PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
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pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
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assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
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PD_BUS_ACLK_HZ && pclk_div < 0x7);
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rk_clrsetreg(&cru->cru_clksel_con[1],
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PD_BUS_PCLK_DIV_MASK << PD_BUS_PCLK_DIV_SHIFT |
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PD_BUS_HCLK_DIV_MASK << PD_BUS_HCLK_DIV_SHIFT |
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PD_BUS_ACLK_DIV0_MASK << PD_BUS_ACLK_DIV0_SHIFT |
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PD_BUS_ACLK_DIV1_MASK << PD_BUS_ACLK_DIV1_SHIFT,
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pclk_div << PD_BUS_PCLK_DIV_SHIFT |
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hclk_div << PD_BUS_HCLK_DIV_SHIFT |
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aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
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0 << 0);
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/*
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* peri clock pll source selection and
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* set up dependent divisors for PCLK/HCLK and ACLK clocks.
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*/
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aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
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assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
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hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ);
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assert((1 << hclk_div) * PERI_HCLK_HZ ==
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PERI_ACLK_HZ && (hclk_div < 0x4));
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pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ);
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assert((1 << pclk_div) * PERI_PCLK_HZ ==
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PERI_ACLK_HZ && (pclk_div < 0x4));
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rk_clrsetreg(&cru->cru_clksel_con[10],
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PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
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PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
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PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
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PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
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pclk_div << PERI_PCLK_DIV_SHIFT |
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hclk_div << PERI_HCLK_DIV_SHIFT |
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aclk_div << PERI_ACLK_DIV_SHIFT);
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/* PLL enter normal-mode */
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rk_clrsetreg(&cru->cru_mode_con,
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GPLL_MODE_MASK << GPLL_MODE_SHIFT |
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CPLL_MODE_MASK << CPLL_MODE_SHIFT,
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GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
|
|
CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
|
|
}
|
|
#endif
|
|
|
|
void rkclk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
|
|
{
|
|
/* pll enter slow-mode */
|
|
rk_clrsetreg(&cru->cru_mode_con,
|
|
APLL_MODE_MASK << APLL_MODE_SHIFT,
|
|
APLL_MODE_SLOW << APLL_MODE_SHIFT);
|
|
|
|
rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
|
|
|
|
/* waiting for pll lock */
|
|
while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK))
|
|
udelay(1);
|
|
|
|
/*
|
|
* core clock pll source selection and
|
|
* set up dependent divisors for MPAXI/M0AXI and ARM clocks.
|
|
* core clock select apll, apll clk = 1800MHz
|
|
* arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
|
|
*/
|
|
rk_clrsetreg(&cru->cru_clksel_con[0],
|
|
CORE_SEL_PLL_MASK << CORE_SEL_PLL_SHIFT |
|
|
A17_DIV_MASK << A17_DIV_SHIFT |
|
|
MP_DIV_MASK << MP_DIV_SHIFT |
|
|
M0_DIV_MASK << M0_DIV_SHIFT,
|
|
0 << A17_DIV_SHIFT |
|
|
3 << MP_DIV_SHIFT |
|
|
1 << M0_DIV_SHIFT);
|
|
|
|
/*
|
|
* set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
|
|
* l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
|
|
*/
|
|
rk_clrsetreg(&cru->cru_clksel_con[37],
|
|
CLK_L2RAM_DIV_MASK << CLK_L2RAM_DIV_SHIFT |
|
|
ATCLK_CORE_DIV_CON_MASK << ATCLK_CORE_DIV_CON_SHIFT |
|
|
PCLK_CORE_DBG_DIV_MASK >> PCLK_CORE_DBG_DIV_SHIFT,
|
|
1 << CLK_L2RAM_DIV_SHIFT |
|
|
3 << ATCLK_CORE_DIV_CON_SHIFT |
|
|
3 << PCLK_CORE_DBG_DIV_SHIFT);
|
|
|
|
/* PLL enter normal-mode */
|
|
rk_clrsetreg(&cru->cru_mode_con,
|
|
APLL_MODE_MASK << APLL_MODE_SHIFT,
|
|
APLL_MODE_NORMAL << APLL_MODE_SHIFT);
|
|
}
|
|
|
|
/* Get pll rate by id */
|
|
static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
|
|
enum rk_clk_id clk_id)
|
|
{
|
|
uint32_t nr, no, nf;
|
|
uint32_t con;
|
|
int pll_id = rk_pll_id(clk_id);
|
|
struct rk3288_pll *pll = &cru->pll[pll_id];
|
|
static u8 clk_shift[CLK_COUNT] = {
|
|
0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
|
|
GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
|
|
};
|
|
uint shift;
|
|
|
|
con = readl(&cru->cru_mode_con);
|
|
shift = clk_shift[clk_id];
|
|
switch ((con >> shift) & APLL_MODE_MASK) {
|
|
case APLL_MODE_SLOW:
|
|
return OSC_HZ;
|
|
case APLL_MODE_NORMAL:
|
|
/* normal mode */
|
|
con = readl(&pll->con0);
|
|
no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
|
|
nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
|
|
con = readl(&pll->con1);
|
|
nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
|
|
|
|
return (24 * nf / (nr * no)) * 1000000;
|
|
case APLL_MODE_DEEP:
|
|
default:
|
|
return 32768;
|
|
}
|
|
}
|
|
|
|
static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
|
|
int periph)
|
|
{
|
|
uint src_rate;
|
|
uint div, mux;
|
|
u32 con;
|
|
|
|
switch (periph) {
|
|
case HCLK_EMMC:
|
|
con = readl(&cru->cru_clksel_con[12]);
|
|
mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
|
|
div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
|
|
break;
|
|
case HCLK_SDMMC:
|
|
con = readl(&cru->cru_clksel_con[11]);
|
|
mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
|
|
div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
|
|
break;
|
|
case HCLK_SDIO0:
|
|
con = readl(&cru->cru_clksel_con[12]);
|
|
mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK;
|
|
div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
|
|
return DIV_TO_RATE(src_rate, div);
|
|
}
|
|
|
|
static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
|
|
int periph, uint freq)
|
|
{
|
|
int src_clk_div;
|
|
int mux;
|
|
|
|
debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
|
|
src_clk_div = RATE_TO_DIV(gclk_rate, freq);
|
|
|
|
if (src_clk_div > 0x3f) {
|
|
src_clk_div = RATE_TO_DIV(OSC_HZ, freq);
|
|
mux = EMMC_PLL_SELECT_24MHZ;
|
|
assert((int)EMMC_PLL_SELECT_24MHZ ==
|
|
(int)MMC0_PLL_SELECT_24MHZ);
|
|
} else {
|
|
mux = EMMC_PLL_SELECT_GENERAL;
|
|
assert((int)EMMC_PLL_SELECT_GENERAL ==
|
|
(int)MMC0_PLL_SELECT_GENERAL);
|
|
}
|
|
switch (periph) {
|
|
case HCLK_EMMC:
|
|
rk_clrsetreg(&cru->cru_clksel_con[12],
|
|
EMMC_PLL_MASK << EMMC_PLL_SHIFT |
|
|
EMMC_DIV_MASK << EMMC_DIV_SHIFT,
|
|
mux << EMMC_PLL_SHIFT |
|
|
(src_clk_div - 1) << EMMC_DIV_SHIFT);
|
|
break;
|
|
case HCLK_SDMMC:
|
|
rk_clrsetreg(&cru->cru_clksel_con[11],
|
|
MMC0_PLL_MASK << MMC0_PLL_SHIFT |
|
|
MMC0_DIV_MASK << MMC0_DIV_SHIFT,
|
|
mux << MMC0_PLL_SHIFT |
|
|
(src_clk_div - 1) << MMC0_DIV_SHIFT);
|
|
break;
|
|
case HCLK_SDIO0:
|
|
rk_clrsetreg(&cru->cru_clksel_con[12],
|
|
SDIO0_PLL_MASK << SDIO0_PLL_SHIFT |
|
|
SDIO0_DIV_MASK << SDIO0_DIV_SHIFT,
|
|
mux << SDIO0_PLL_SHIFT |
|
|
(src_clk_div - 1) << SDIO0_DIV_SHIFT);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return rockchip_mmc_get_clk(cru, gclk_rate, periph);
|
|
}
|
|
|
|
static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
|
|
int periph)
|
|
{
|
|
uint div, mux;
|
|
u32 con;
|
|
|
|
switch (periph) {
|
|
case SCLK_SPI0:
|
|
con = readl(&cru->cru_clksel_con[25]);
|
|
mux = (con >> SPI0_PLL_SHIFT) & SPI0_PLL_MASK;
|
|
div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
|
|
break;
|
|
case SCLK_SPI1:
|
|
con = readl(&cru->cru_clksel_con[25]);
|
|
mux = (con >> SPI1_PLL_SHIFT) & SPI1_PLL_MASK;
|
|
div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
|
|
break;
|
|
case SCLK_SPI2:
|
|
con = readl(&cru->cru_clksel_con[39]);
|
|
mux = (con >> SPI2_PLL_SHIFT) & SPI2_PLL_MASK;
|
|
div = (con >> SPI2_DIV_SHIFT) & SPI2_DIV_MASK;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
assert(mux == SPI0_PLL_SELECT_GENERAL);
|
|
|
|
return DIV_TO_RATE(gclk_rate, div);
|
|
}
|
|
|
|
static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
|
|
int periph, uint freq)
|
|
{
|
|
int src_clk_div;
|
|
|
|
debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
|
|
src_clk_div = RATE_TO_DIV(gclk_rate, freq);
|
|
switch (periph) {
|
|
case SCLK_SPI0:
|
|
rk_clrsetreg(&cru->cru_clksel_con[25],
|
|
SPI0_PLL_MASK << SPI0_PLL_SHIFT |
|
|
SPI0_DIV_MASK << SPI0_DIV_SHIFT,
|
|
SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
|
|
src_clk_div << SPI0_DIV_SHIFT);
|
|
break;
|
|
case SCLK_SPI1:
|
|
rk_clrsetreg(&cru->cru_clksel_con[25],
|
|
SPI1_PLL_MASK << SPI1_PLL_SHIFT |
|
|
SPI1_DIV_MASK << SPI1_DIV_SHIFT,
|
|
SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
|
|
src_clk_div << SPI1_DIV_SHIFT);
|
|
break;
|
|
case SCLK_SPI2:
|
|
rk_clrsetreg(&cru->cru_clksel_con[39],
|
|
SPI2_PLL_MASK << SPI2_PLL_SHIFT |
|
|
SPI2_DIV_MASK << SPI2_DIV_SHIFT,
|
|
SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
|
|
src_clk_div << SPI2_DIV_SHIFT);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return rockchip_spi_get_clk(cru, gclk_rate, periph);
|
|
}
|
|
|
|
static ulong rk3288_clk_get_rate(struct clk *clk)
|
|
{
|
|
struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
|
|
ulong new_rate, gclk_rate;
|
|
|
|
gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
|
|
switch (clk->id) {
|
|
case 0 ... 63:
|
|
new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
|
|
break;
|
|
case HCLK_EMMC:
|
|
case HCLK_SDMMC:
|
|
case HCLK_SDIO0:
|
|
new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
|
|
break;
|
|
case SCLK_SPI0:
|
|
case SCLK_SPI1:
|
|
case SCLK_SPI2:
|
|
new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);
|
|
break;
|
|
case PCLK_I2C0:
|
|
case PCLK_I2C1:
|
|
case PCLK_I2C2:
|
|
case PCLK_I2C3:
|
|
case PCLK_I2C4:
|
|
case PCLK_I2C5:
|
|
return gclk_rate;
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
|
|
return new_rate;
|
|
}
|
|
|
|
static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
|
|
{
|
|
struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
|
|
struct rk3288_cru *cru = priv->cru;
|
|
ulong new_rate, gclk_rate;
|
|
|
|
gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
|
|
switch (clk->id) {
|
|
case CLK_DDR:
|
|
new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
|
|
break;
|
|
case HCLK_EMMC:
|
|
case HCLK_SDMMC:
|
|
case HCLK_SDIO0:
|
|
new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
|
|
break;
|
|
case SCLK_SPI0:
|
|
case SCLK_SPI1:
|
|
case SCLK_SPI2:
|
|
new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
|
|
break;
|
|
#ifndef CONFIG_SPL_BUILD
|
|
case SCLK_MAC:
|
|
new_rate = rockchip_mac_set_clk(priv->cru, clk->id, rate);
|
|
break;
|
|
case DCLK_VOP0:
|
|
case DCLK_VOP1:
|
|
new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
|
|
break;
|
|
case SCLK_EDP_24M:
|
|
/* clk_edp_24M source: 24M */
|
|
rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
|
|
|
|
/* rst edp */
|
|
rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
|
|
udelay(1);
|
|
rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
|
|
new_rate = rate;
|
|
break;
|
|
case ACLK_VOP0:
|
|
case ACLK_VOP1: {
|
|
u32 div;
|
|
|
|
/* vop aclk source clk: cpll */
|
|
div = CPLL_HZ / rate;
|
|
assert((div - 1 < 64) && (div * rate == CPLL_HZ));
|
|
|
|
switch (clk->id) {
|
|
case ACLK_VOP0:
|
|
rk_clrsetreg(&cru->cru_clksel_con[31],
|
|
3 << 6 | 0x1f << 0,
|
|
0 << 6 | (div - 1) << 0);
|
|
break;
|
|
case ACLK_VOP1:
|
|
rk_clrsetreg(&cru->cru_clksel_con[31],
|
|
3 << 14 | 0x1f << 8,
|
|
0 << 14 | (div - 1) << 8);
|
|
break;
|
|
}
|
|
new_rate = rate;
|
|
break;
|
|
}
|
|
case PCLK_HDMI_CTRL:
|
|
/* enable pclk hdmi ctrl */
|
|
rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
|
|
|
|
/* software reset hdmi */
|
|
rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
|
|
udelay(1);
|
|
rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
|
|
new_rate = rate;
|
|
break;
|
|
#endif
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
|
|
return new_rate;
|
|
}
|
|
|
|
static struct clk_ops rk3288_clk_ops = {
|
|
.get_rate = rk3288_clk_get_rate,
|
|
.set_rate = rk3288_clk_set_rate,
|
|
};
|
|
|
|
static int rk3288_clk_probe(struct udevice *dev)
|
|
{
|
|
struct rk3288_clk_priv *priv = dev_get_priv(dev);
|
|
|
|
priv->cru = (struct rk3288_cru *)dev_get_addr(dev);
|
|
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
|
|
#ifdef CONFIG_SPL_BUILD
|
|
rkclk_init(priv->cru, priv->grf);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rk3288_clk_bind(struct udevice *dev)
|
|
{
|
|
int ret;
|
|
|
|
/* The reset driver does not have a device node, so bind it here */
|
|
ret = device_bind_driver(gd->dm_root, "rk3288_sysreset", "reset", &dev);
|
|
if (ret)
|
|
debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id rk3288_clk_ids[] = {
|
|
{ .compatible = "rockchip,rk3288-cru" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(clk_rk3288) = {
|
|
.name = "clk_rk3288",
|
|
.id = UCLASS_CLK,
|
|
.of_match = rk3288_clk_ids,
|
|
.priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
|
|
.ops = &rk3288_clk_ops,
|
|
.bind = rk3288_clk_bind,
|
|
.probe = rk3288_clk_probe,
|
|
};
|